Gate coupling in floating-gate memory cells

Abstract

Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.

1 . A floating-gate memory cell, comprising: 
 a tunnel dielectric layer overlying a semiconductor substrate and interposed between first and second isolation regions;    a floating-gate layer overlying the tunnel dielectric layer and at least a portion of the isolation regions, wherein the floating-gate layer comprises first and second lower sidewalls overlying the first and second isolation regions, respectively, and first and second upper sidewalls set back from the first and second lower sidewalls, respectively;    an intergate dielectric layer overlying the floating-gate layer; and    a control-gate layer overlying the intergate dielectric layer.    
   
   
       2 . The floating-gate memory cell of  claim 1 , wherein the first and second upper sidewalls are substantially aligned with edges of the first and second isolation regions, respectively.  
   
   
       3 . The floating-gate memory cell of  claim 1 , wherein the lower sidewalls have a height that is less than or equal to a height of the upper sidewalls.  
   
   
       4 . The floating-gate memory cell of  claim 3 , wherein the height of the upper sidewalls is approximately 1 to 3 times the height of the lower sidewalls.  
   
   
       5 . The floating-gate memory cell of  claim 1 , wherein the floating-gate layer comprises one or more layers of material capable of storing a charge.  
   
   
       6 . The floating-gate memory cell of  claim 5 , wherein the floating-gate layer comprises first and second polysilicon layers.  
   
   
       7 . The floating-gate memory cell of  claim 1 , wherein the floating-gate memory cell is arranged and configured as part of a NAND array of memory cells.  
   
   
       8 . A floating-gate memory cell, comprising: 
 a tunnel dielectric layer overlying a semiconductor substrate;    a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer has a stepped profile with an upper portion set back from a lower portion;    an intergate dielectric layer overlying the floating-gate layer; and    a control-gate layer overlying the intergate dielectric layer.    
   
   
       9 . The floating-gate memory cell of  claim 8 , wherein the lower portion of the floating-gate layer is in closer proximity to a lower portion of a floating-gate layer of an adjacent floating-gate memory cell than the upper portion of the floating-gate layer is in relation to an upper portion of the floating-gate layer of the adjacent floating-gate memory cell.  
   
   
       10 . The floating-gate memory cell of  claim 8 , wherein the tunnel dielectric layer is a silicon oxide layer.  
   
   
       11 . The floating-gate memory cell of  claim 10 , wherein the silicon oxide layer is thermally grown on a monocrystalline silicon substrate.  
   
   
       12 . The floating-gate memory cell of  claim 8 , wherein the floating-gate layer is overlying and adjoining the tunnel dielectric layer.  
   
   
       13 . The floating-gate memory cell of  claim 8 , wherein the floating-gate layer comprises more than one layer of material.  
   
   
       14 . The floating-gate memory cell of  claim 13 , wherein the floating-gate layer comprises a first polysilicon layer adjoining the tunnel dielectric layer and interposed between two isolation regions, and a second polysilicon layer adjoining the first polysilicon layer and overlying at least a portion of each of the two isolation regions.  
   
   
       15 . The floating-gate memory cell of  claim 14 , wherein the first and second polysilicon layers are each conductively doped at a time selected from the group consisting of during formation and after formation.  
   
   
       16 . The floating-gate memory cell of  claim 8 , wherein the intergate dielectric layer is overlying and adjoining the floating-gate layer.  
   
   
       17 . The floating-gate memory cell of  claim 8 , wherein the intergate dielectric layer comprises more than one layer of dielectric material.  
   
   
       18 . The floating-gate memory cell of  claim 8 , wherein the control-gate layer is overlying and adjoining the intergate dielectric layer.  
   
   
       19 . The floating-gate memory cell of  claim 8 , wherein the control-gate layer comprises more than one layer of conductive material.  
   
   
       20 . The floating-gate memory cell of  claim 8 , wherein the floating-gate memory cell is arranged and configured as part of a NAND array of memory cells.  
   
   
       21 . A memory device, comprising: 
 an array of floating-gate memory cells; and    circuitry for control and/or access of the array of floating-gate memory cells;    wherein the at least one memory cell of the array of floating-gate memory cells comprises: 
 a tunnel dielectric layer overlying a semiconductor substrate and interposed between first and second isolation regions;  
 a floating-gate layer overlying the tunnel dielectric layer and at least a portion of the isolation regions, wherein the floating-gate layer comprises first and second lower sidewalls overlying the first and second isolation regions, respectively, and first and second upper sidewalls set back from the first and second lower sidewalls, respectively;  
 an intergate dielectric layer overlying the floating-gate layer; and  
 a control-gate layer overlying the intergate dielectric layer.  
   
   
   
       22 . The memory device of  claim 21 , wherein the array of floating-gate memory cells are arranged and configured as a NAND array of floating-gate memory cells.  
   
   
       23 . A memory device, comprising: 
 an array of floating-gate memory cells; and    circuitry for control and/or access of the array of floating-gate memory cells;    wherein the at least one memory cell of the array of floating-gate memory cells comprises: 
 a tunnel dielectric layer overlying a semiconductor substrate;  
 a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer has a stepped profile with an upper portion set back from a lower portion;  
 an intergate dielectric layer overlying the floating-gate layer; and  
 a control-gate layer overlying the intergate dielectric layer.  
   
   
   
       24 . The memory device of  claim 23 , wherein the array of floating-gate memory cells are arranged and configured as a NAND array of floating-gate memory cells.  
   
   
       25 . An electronic system, comprising: 
 a processor; and    a memory device coupled to the processor, wherein the memory device comprises: 
 an array of floating-gate memory cells, at least one memory cell comprising: 
 a tunnel dielectric layer overlying a semiconductor substrate and interposed between first and second isolation regions;  
 a floating-gate layer overlying the tunnel dielectric layer and at least a portion of the isolation regions, wherein the floating-gate layer comprises first and second lower sidewalls overlying the first and second isolation regions, respectively, and first and second upper sidewalls set back from the first and second lower sidewalls, respectively;  
 an intergate dielectric layer overlying the floating-gate layer; and  
 a control-gate layer overlying the intergate dielectric layer; and  
 
 circuitry for control and/or access of the array of floating-gate memory cells.  
   
   
   
       26 . An electronic system, comprising: 
 a processor; and    a memory device coupled to the processor, wherein the memory device comprises: 
 an array of floating-gate memory cells, at least one memory cell comprising: 
 a tunnel dielectric layer overlying a semiconductor substrate;  
 a floating-gate layer overlying the tunnel dielectric layer, wherein the floating-gate layer has a stepped profile with an upper portion set back from a lower portion;  
 an intergate dielectric layer overlying the floating-gate layer; and  
 a control-gate layer overlying the intergate dielectric layer; and  
 circuitry for control and/or access of the array of floating-gate memory cells.