Methods for forming semiconductor structures with differential surface layer thicknesses

Abstract

A semiconductor structure having a substrate with a surface layer including strained silicon. The surface layer has a first region with a first thickness less than a second thickness of a second region. A gate dielectric layer is disposed over a portion of at least the first surface layer region.

1 .- 24 . (canceled)  
     
     
         25 . A method for forming a semiconductor structure, the method comprising the steps of: 
 providing a substrate having a surface layer disposed thereon, the surface layer comprising strained silicon;    selectively forming a sacrificial layer in a portion of the surface layer; and    substantially removing the sacrificial layer to define a first region of the surface layer having a first thickness and a second region of the surface layer having a second thickness,    wherein the first thickness is less than the second thickness.    
     
     
         26 . The method of  claim 25  further comprising: 
 prior to forming the sacrificial layer, forming a masking layer over the surface layer; and    removing a portion of the masking layer to expose the portion of the surface layer,    wherein the sacrificial layer is subsequently selectively formed in the portion of the surface layer exposed by the masking layer.    
     
     
         27 . The method of  claim 26 , wherein forming the masking layer comprises forming a masking silicon nitride layer.  
     
     
         28 . The method of  claim 27 , wherein forming the masking layer comprises forming a pad silicon dioxide layer prior to forming the masking silicon nitride layer.  
     
     
         29 . The method of  claim 25  further comprising: 
 forming a first source and a first drain in the first region of the surface layer, the first source and the first drain including a first type of dopant; and    forming a second source and a second drain in the second region of the surface layer, the second source and the second drain including a second type of dopant.    
     
     
         30 . The method of  claim 29 , wherein the first type of dopant is n-type and the second type of dopant is p-type.  
     
     
         31 . The method of  claim 29 , wherein the first type of dopant is p-type and the second type of dopant is n-type.  
     
     
         32 . The method of  claim 25 , wherein the surface layer is disposed over a relaxed layer.  
     
     
         33 . The method of  claim 32 , wherein the relaxed layer comprises germanium.  
     
     
         34 . The method of  claim 32 , wherein the relaxed layer comprises silicon.  
     
     
         35 . The method of  claim 25 , wherein the surface layer is disposed over an insulator layer.  
     
     
         36 . The method of  claim 25 , wherein the surface layer is disposed over a compressively strained layer.  
     
     
         37 . The method of  claim 36 , wherein the compressively strained layer comprises SiGe.  
     
     
         38 . The method of  claim 36 , wherein the compressively strained layer is disposed over an insulator layer.  
     
     
         39 . The method of  claim 25  further comprising forming a gate dielectric over the first and second regions of the surface layer.  
     
     
         40 . The method of  claim 39 , wherein forming the gate dielectric comprises oxidation.  
     
     
         41 . The method of  claim 39 , wherein forming the gate dielectric comprises deposition.  
     
     
         42 . The method of  claim 41 , wherein the gate dielectric comprises a high-k dielectric.  
     
     
         43 . The method of  claim 25 , wherein providing the substrate comprises wafer bonding.