PCI Express system and method of transitioning link state thereof

Abstract

A PCI Express system and a method of transitioning link state thereof are provided. The PCI Express system has an upstream device, a downstream device and a link. The upstream device and the downstream device transmit data packets to both via the link, but when the link is in a first link state, data packet transmission is forbidden. In the beginning, the link is in a second link state and data packet transmission is normal. The upstream device transmits a data packet via the link to the downstream device. A time period is counted when receiving the data packet. The downstream device asserts an acknowledge packet to the upstream device to response the data pocket. After the timer is expired, the link is transited to the first link state.

1 . A method of transitioning link state, for a link connected between an upstream device and a downstream device, wherein an initial link state of the link is in a first link state, and the downstream device is in an abnormal operation state, the method comprising: 
 transitioning the link state from the first link state to a second link state;    asserting a data packet by the upstream device;    counting a time period when the downstream device receives the data packet;    asserting an acknowledge packet by the downstream device to the upstream device as a response to the data packet;    asserting a power entering packet by the downstream device to the upstream device when the time period is expired; and    asserting a power request acknowledge packet by the upstream device to respond to the power entering packet so as to transit the link from the second link state to the first link state.    
   
   
       2 . The method of  claim 1  wherein the data packet is a Transaction Layer Packet (TLP); the power entering packet and the power request acknowledge packet are respectively Data Link Layer Packets (DLLPs).  
   
   
       3 . The method of  claim 1  wherein the time period is not less than one data packet transmission period plus 10 cycles.  
   
   
       4 . The method of  claim 3  wherein the time period further comprises 32 QW TLPs transmission period.  
   
   
       5 . The method of  claim 1  wherein the time period ensures the upstream device receives the acknowledge packet earlier than the power entering packet  
   
   
       6 . The method of  claim 1  wherein the first link state is the link state L 0 .  
   
   
       7 . The method of  claim 1  wherein the second link state is the link state L 1 .  
   
   
       8 . The method of  claim 1  wherein the upstream device is a Root Complex and the downstream device is an End Point.  
   
   
       9 . The method of  claim 1  wherein the method is applied to a PCI Express link.  
   
   
       10 . A data transmission system comprising: 
 an upstream device, for asserting a data packet;    a downstream device, a time period is counted when the downstream device receives the data packet from the upstream device, at the same time, the downstream device asserts an acknowledge packet to the upstream device; and    a link, connected between the upstream device and the downstream device for data transmission;    wherein the downstream device asserts a power entering packet to the upstream device when the time period is expired and the time period ensures the acknowledge packet is received earlier than power entering packet.    
   
   
       11 . The system of  claim 10  wherein an initial link state of the link is at L 1  state.  
   
   
       12 . The system of  claim 11  wherein the link is transited to the link state L 0  before transmitting the data packet.  
   
   
       13 . The system of  claim 12  wherein the upstream device asserts a power request acknowledge packet to the downstream device as a response to the power entering packet, and the link is transited to L 1  state.  
   
   
       14 . The system of  claim 10  wherein the initial link state of the downstream device is in an abnormal operation state.  
   
   
       15 . The system of  claim 10  wherein the data packet is utilized to change or read the state of the downstream device.  
   
   
       16 . The system of  claim 10  wherein the time period is not less than one data packet transmission period plus 10 cycles.  
   
   
       17 . The system of  claim 16  wherein the time period further comprises 32 QW TLPs transmission period.  
   
   
       18 . The system of  claim 10  wherein the data transmission system is a PCI Express system.  
   
   
       19 . A method of link data transmission, for a link connected between an upstream device and a downstream device; wherein a initial link state of the link is unable to transmit data packets; the downstream device is in an abnormal operation state, the method comprising: 
 asserting a data packet by the upstream device;    counting a time period when the downstream device receives the data packet;    asserting an acknowledge packet by the downstream device to the upstream device as a response to the data packet; and    asserting a power entry packet by the downstream device to the upstream device when the time period is expired;    wherein the time period ensures the acknowledge packet is received earlier than the power entry packet    
   
   
       20 . The method of  claim 19  wherein the method further comprising: 
 transiting the link state to a state able to transmit data packet.    
   
   
       21 . The method of  claim 20  wherein the method further comprising: 
 asserting a power request acknowledge packet responding to the power entering packet by the upstream device so as to transit the link state to a state unable to transmit data packet.    
   
   
       22 . The method of  claim 19  wherein the time period is not less than one data packet transmission period plus 10 cycles.  
   
   
       23 . The method of  claim 22  wherein the time period further comprises 32 QW TLPs transmission period.  
   
   
       24 . The method of  claim 19  wherein the method is applied to a PCI Express system.