Virtual register set expanding processor internal storage

Abstract

A processor includes a set of registers implemented internal to the processor and plural virtual registers. The set of registers are each individually addressable using a corresponding register identification and the plural virtual registers are each individually addressable using a corresponding virtual register identification. At least one of the virtual registers is an auxiliary register implemented internal to the processor. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation.

1 . A processor, comprising: 
 a set of registers implemented internal to the processor, each individually addressable by register operations executing on the processor using a corresponding register identification; and    plural virtual registers, each individually addressable by virtual register operations executing on the processor using a corresponding virtual register identification, wherein at least one of the virtual registers is an auxiliary register implemented internal to the processor, and wherein the processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation.    
   
   
       2 . The processor of  claim 1 , wherein less than all of an available virtual register space is implemented by a particular instance of the processor, and wherein at least some unimplemented virtual registers are accessed utilizing a trap and emulate operation.  
   
   
       3 . The processor of  claim 1 , wherein the register operations, the virtual register operations and the transfer operation correspond to instructions of an instruction set of the processor.  
   
   
       4 . The processor of  claim 1 , wherein the transfer operation is an instruction of an instruction set of the processor.  
   
   
       5 . The processor of  claim 1 , further comprising: 
 a virtual register cache configured to store multiple sets of virtual register values, wherein each of the multiple sets of virtual register values corresponds to a different context, and wherein the virtual register cache is integrated into a data cache that also stores multiple sets of values of the set of registers.    
   
   
       6 . The processor of  claim 1 , wherein each of the plural virtual registers includes a valid bit that is reset on a context switch and set when a value is loaded from the virtual register cache.  
   
   
       7 . The processor of  claim 1 , further comprising a virtual register translation look-aside buffer for tracking the location of each set of virtual register values associated with each context.  
   
   
       8 . The processor of  claim 1 , wherein the transfer operation includes a computation of a new value.  
   
   
       9 . The processor of  claim 1 , wherein all of the virtual registers are implemented internal to the processor, and wherein the processor, the set of registers and the virtual registers are included within a single integrated circuit.  
   
   
       10 . Software encoded in one or more computer readable storage media, the software comprising: 
 a sequence of instructions for a processor,    the sequence including one or more instructions that address a particular register of the processor and operate on a value stored therein,    wherein at least one of the instructions directs the processor to transfer a value between the particular register and a virtual register of the processor, and wherein at least one other of the instructions directs the processor to copy a set of virtual register values between a set of virtual registers and a virtual register cache, where the set of virtual register values corresponds to a particular context of the processor.    
   
   
       11 . The software of  claim 10 , wherein the virtual register is unimplemented and at least one of the instructions causes the processor to generate a trap operation to emulate the transfer of the value from the particular register to the virtual register.  
   
   
       12 . The software of  claim 10 , wherein the copying is from the set of virtual registers to the virtual register cache.  
   
   
       13 . The software of  claim 10 , wherein the copying is from the virtual register cache to the set of virtual registers.  
   
   
       14 . The software of  claim 10 , wherein the transfer is from the virtual register to the particular register.  
   
   
       15 . The software of  claim 10 , wherein the transfer is from the particular register to the virtual register.  
   
   
       16 . The software of  claim 10 , wherein at least one of the virtual registers of the set of virtual registers is implemented internal to the processor.  
   
   
       17 . The software of  claim 10 , wherein all of the virtual registers of the set of virtual registers are implemented internal to the processor.  
   
   
       18 . A method of operating a processor comprising: 
 executing an instruction sequence, wherein a first instruction stores a value in a register in a local register set implemented internal to the processor and a second instruction copies the value from the register in the local register set to a virtual register in a virtual register set, and wherein the virtual register is implemented internal to the processor; and    employing a virtual register cache to store multiple sets of virtual register values, wherein each of the sets of virtual register values correspond to a different context of the processor,    wherein a register identification field of the second instruction identifies the register in the local register set and a virtual register identification field of the second instruction identifies the virtual register in the virtual register set.    
   
   
       19 . The method of  claim 18 , wherein the virtual register set contains unimplemented registers, and wherein a trap and emulate operation is initiated upon accessing one of the unimplemented registers.  
   
   
       20 . The method of  claim 18 , wherein at least one of the virtual registers of the virtual register set is implemented internal to the processor.  
   
   
       21 . The method of  claim 18 , wherein all of the virtual registers of the virtual register set are implemented internal to the processor, and wherein the processor, the set of registers and the virtual registers are included within a single integrated circuit.