DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators

Abstract

Methods for forming structures and systems including memory cells having a volatile and a non-volatile component in a single memory cell are provided. The formed memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to one of the first and the second source/drain regions. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The formed memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.

1 . A method of forming a memory, comprising: 
 forming a memory cell including: 
 forming a source region and a drain region separated by a channel region in a substrate;  
 forming a storage capacitor coupled to one of the source and drain regions;  
 forming a gate oxide on the channel region, the gate oxide having a first tunneling barrier height;  
 forming a floating gate opposing the channel region, the floating gate separated from the channel region by the gate oxide;  
 forming a control gate opposing the floating gate; and  
 forming a metal oxide insulator separating the control gate from the floating gate, the metal oxide insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height; and  
   adapting the memory to operate the memory cell in a volatile memory mode and in a non-volatile memory mode.    
   
   
       2 . The method of  claim 1 , wherein forming a metal oxide insulator includes forming a transition metal oxide insulator.  
   
   
       3 . The method of  claim 1 , wherein forming a metal oxide insulator includes forming aluminum oxide.  
   
   
       4 . The method of  claim 1 , wherein forming a metal oxide insulator includes forming zirconium oxide.  
   
   
       5 . The method of  claim 1 , wherein forming a metal oxide insulator includes forming lead oxide.  
   
   
       6 . The method of  claim 1 , wherein forming a metal oxide insulator includes forming a Perovskite metal oxide insulator.  
   
   
       7 . The method of  claim 1 , wherein forming a floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the metal oxide insulator.  
   
   
       8 . The method of  claim 1 , wherein forming a control gate includes a forming a polysilicon control gate having a metal layer formed thereon in contact with the metal oxide insulator.  
   
   
       9 . The method of  claim 1 , wherein forming a gate oxide includes forming silicon dioxide having a tunneling barrier height of about 3.2 eV.  
   
   
       10 . The method of  claim 1 , wherein forming a control gate includes forming an edge defined vertical control gate.  
   
   
       11 . A method of forming a memory, comprising: 
 forming an array of memory cells, wherein forming each memory cell includes:    forming a source region and a drain region separated by a channel region in a substrate; 
 forming a storage capacitor coupled to the drain region;  
 forming a floating gate opposing the channel region;  
 forming a gate oxide separating the floating gate from the channel region, the gate oxide having a first tunneling barrier height;  
 forming a first metal layer separating the metal oxide insulator and the floating gate, the first metal layer in contact with the floating gate;  
 forming a control gate opposing the floating gate; and  
 forming a metal oxide insulator separating the control gate from the floating gate, the metal oxide insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height;  
   forming a number of bit lines coupled to the source regions along a first direction in the array of memory cells;    a number of word lines coupled to the control gates along a second direction in the array of memory cells; and    adapting the memory to operate each memory cell in the array of memory cells in a volatile memory mode and in a non-volatile memory mode.    
   
   
       12 . The method of  claim 11 , wherein adapting the memory to operate each memory cell includes adapting the memory to control each memory cell to access a first charge representing a data value from the storage capacitor in the volatile memory mode and a second charge representing a data value from the floating gate in the non-volatile memory mode, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.  
   
   
       13 . The method of  claim 11 , wherein the method further includes forming a second metal layer on the control gate, the second metal layer in contact with the metal oxide insulator.  
   
   
       14 . The method of  claim 13 , wherein forming a floating gate includes forming a polysilicon floating gate.  
   
   
       15 . The method of  claim 14 , wherein forming a gate oxide includes forming silicon oxide having a tunneling barrier height of about 3.2 eV.  
   
   
       16 . The method of  claim 15 , wherein forming a metal oxide insulator includes forming a transition metal oxide.  
   
   
       17 . The method of  claim 15 , wherein forming a metal oxide insulator includes forming titanium oxide.  
   
   
       18 . The method of  claim 15 , wherein forming a metal oxide insulator includes forming tantalum oxide.  
   
   
       19 . The method of  claim 15 , wherein forming a metal oxide insulator includes forming niobium oxide.  
   
   
       20 . The method of  claim 15 , wherein forming a metal oxide insulator includes forming a Perovskite metal oxide insulator.  
   
   
       21 . The method of  claim 15 , wherein forming a source region and a drain region includes forming a n+ source region and a n+ drain region.  
   
   
       22 . The method of  claim 15 , wherein the forming a control gate lines includes forming a forming a vertical control gate.  
   
   
       23 . The method of  claim 15 , wherein the forming a control gate lines includes forming a forming an edge defined vertical control gate.  
   
   
       24 . A method of forming an electronic system, comprising: 
 providing a processor; and    coupling the processor to a memory, the memory formed by a method including: 
 forming a memory cell, the memory cell formed by:  
 forming a source region and a drain region separated by a channel region in a substrate;  
 forming a storage capacitor coupled to one of the source and drain regions;  
 forming a gate oxide on the channel region, the gate oxide having a first tunneling barrier height;  
 forming a floating gate opposing the channel region, the floating gate separated from the channel region by the gate oxide;  
 forming a control gate opposing the floating gate; and  
 forming a metal oxide insulator separating the control gate from the floating gate, the metal oxide insulator having a second tunneling barrier height, the second tunneling barrier height being less than the first tunneling barrier height; and  
 adapting the memory to operate the memory cell in a volatile memory mode and in a non-volatile memory mode.  
   
   
   
       25 . The method of  claim 24 , wherein adapting the memory to operate the memory cell includes adapting the memory to control the memory cell to access a first charge representing a data value from the storage capacitor in the volatile memory mode and a second charge representing a data value from the floating gate in the non-volatile memory mode, wherein the first charge is accessible without affecting the second charge and the second charge is accessible without affecting the first charge.  
   
   
       26 . The method of  claim 24 , wherein the method further includes forming a first metal layer on the floating gate, the first metal layer in contact with the metal oxide insulator.  
   
   
       27 . The method of  claim 26 , wherein forming a gate oxide includes forming silicon dioxide having a tunneling barrier height of about 3.2 eV.  
   
   
       28 . The method of  claim 27 , wherein forming a floating oxide includes forming a polysilicon floating gate and forming a control gate includes forming a polysilicon control gate.  
   
   
       29 . The method of  claim 26 , wherein the method further includes forming a second metal layer on the control gate, the second metal layer in contact with the metal oxide insulator.  
   
   
       30 . The method of  claim 26 , wherein forming a metal oxide insulator includes forming a transition metal oxide insulator.  
   
   
       31 . The method of  claim 26 , wherein forming a metal oxide insulator includes forming aluminum oxide.  
   
   
       32 . The method of  claim 26 , wherein forming a metal oxide insulator includes forming zirconium oxide.  
   
   
       33 . The method of  claim 26 , wherein forming a metal oxide insulator includes forming lead oxide.  
   
   
       34 . The method of  claim 26 , wherein forming a metal oxide insulator includes forming a Perovskite metal oxide insulator.