Methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cell

Abstract

The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

1 . A method of electrically interconnecting different elevation conductive structures, comprising: 
 forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate;    growing a nanowhisker from the first electrically conductive surface, and providing the nanowhisker to be electrically conductive;    providing electrically insulative material about the nanowhisker; and    depositing an electrically conductive material over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and providing the electrically conductive material into a second conductive structure.    
   
   
       2 . The method of  claim 1  wherein the first conductive structure comprises a diffusion region formed in crystalline silicon.  
   
   
       3 . The method of  claim 2  wherein the crystalline silicon comprises bulk monocyrstalline silicon.  
   
   
       4 . The method of  claim 1  wherein the nanowhisker is electrically conductive upon its growth.  
   
   
       5 . The method of  claim 4  wherein the nanowhisker is provided to be electrically conductive at least in part by doping with a conductivity enhancing dopant during said growing.  
   
   
       6 . The method of  claim 1  wherein the nanowhisker is provided to be electrically conductive after its growth.  
   
   
       7 . The method of  claim 6  wherein the nanowhisker is provided to be electrically conductive at least in part by doping with a conductivity enhancing dopant after its growth.  
   
   
       8 . The method of  claim 1  wherein the electrically insulative material contacts the nanowhisker, and the electrically conductive material is deposited on the electrically insulative material which contacts the nanowhisker.  
   
   
       9 . The method of  claim 1  wherein the electrically insulative material is provided about the nanowhisker after its growth.  
   
   
       10 . The method of  claim 9  wherein the electrically insulative material contacts the nanowhisker, and the electrically conductive material is deposited on the electrically insulative material which contacts the nanowhisker.  
   
   
       11 . The method of  claim 9  wherein providing the electrically insulative material comprises depositing said insulative material over the nanowhisker, followed by polishing said insulative material effective to expose the nanowhisker.  
   
   
       12 . The method of  claim 1  wherein the providing of the electrically insulative material comprises depositing said electrically insulative material over the substrate, and forming an opening within the electrically insulative material to the first electrically conductive surface prior to growth of the nanowhisker.  
   
   
       13 . The method of  claim 12  wherein the electrically insulative material contacts the nanowhisker, and the electrically conductive material is deposited on the electrically insulative material which contacts the nanowhisker.  
   
   
       14 . The method of  claim 1  comprising removing some of the grown nanowhisker prior to depositing the electrically conductive material.  
   
   
       15 . The method of  claim 1  wherein the second electrically conductive structure comprises a conductive line.  
   
   
       16 . The method of  claim 1  wherein the nanowhisker during growth comprises a catalytic material that remains as part of a finished circuitry construction comprising the nanowhisker.  
   
   
       17 . The method of  claim 1  wherein the nanowhisker during growth comprises a catalytic material, and comprising removing the catalytic material prior to depositing said electrically conductive material.  
   
   
       18 . A method of forming a capacitor, comprising: 
 growing a nanowhisker from a surface of a substrate, and providing the nanowhisker to be electrically conductive, the nanowhisker comprising sidewalls and comprising a first capacitor electrode;    forming a capacitor dielectric layer over the nanowhisker sidewalls; and    forming a second capacitor electrode over the capacitor dielectric layer.    
   
   
       19 . A method of forming a capacitor, comprising: 
 growing a nanowhisker from a surface of a substrate, and providing the nanowhisker to be electrically conductive;    forming a container-shaped first capacitor electrode in electrical contact with the nanowhisker;    forming a capacitor dielectric layer over the container-shaped first capacitor electrode; and    forming a second capacitor electrode over the capacitor dielectric layer.    
   
   
       20 . A method of forming an interconnect between a substrate bit line contact and a bit line in DRAM, comprising: 
 forming a bit line contact intermediate a pair of wordlines over a semiconductor substrate;    growing a nanowhisker from the bit line contact, and providing the nanowhisker to be electrically conductive; and    forming a bit line in electrical contact with the nanowhisker.    
   
   
       21 . A method of forming a DRAM memory cell, comprising: 
 forming a wordline over a semiconductor substrate, and forming a capacitor storage node contact proximate the wordline;    growing a nanowhisker from the capacitor storage node contact, and providing the nanowhisker to be electrically conductive; and    forming a capacitor dielectric layer and an outer capacitor electrode layer over the nanowhisker.    
   
   
       22 . A method of forming a DRAM memory cell, comprising: 
 forming a wordline over a semiconductor substrate, and forming a bit line contact and a capacitor storage node contact proximate the wordline;    growing a first nanowhisker from the bit line contact and a second nanowhisker from the capacitor storage node contact, and providing the first and second nanowhiskers to be electrically conductive;    forming a bit line in electrical contact with the first nanowhisker; and    forming a capacitor dielectric layer and an outer capacitor electrode layer over the second nanowhisker.