Methods of enabling polysilicon gate electrodes for high-k gate dielectrics

Abstract

Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an optional interfacial oxide, such as SiO 2 or oxy-nitride, to overlay a semiconductor substrate which will be conductively doped for PMOS and NMOS regions. Then a dielectric possessing a high dielectric constant of least seven or greater (also referred to as a high-k dielectric) is deposited on the interfacial oxide. The high-k dielectric is covered with a thin monolayer of metal oxide (i.e., aluminum oxide, Al 2 O 3 ) that is removed from the NMOS regions, but remains in the PMOS regions. The resulting NMOS transistor diffusion regions contain predominately metal to silicon bonds that create predominately Fermi level pinning near the valence band while the resulting PMOS transistor diffusion regions contain metal to silicon bonds that create predominately Fermi level pinning near the conduction band.

1 . A complementary transistor pair on a semiconductor assembly comprising: 
 an NMOS transistor comprising first metal-silicon bonds that create predominately Fermi level pinning near the valance band; and    a PMOS transistor comprising second metal-silicon bonds that create predominately Fermi level pinning near the conductive band.    
   
   
       2 . The complementary transistor pair of  claim 1 , wherein the first metal-silicon bonds comprise hafnium-silicon bonds.  
   
   
       3 . The complementary transistor pair of  claim 1 , wherein the second metal-silicon bonds comprise aluminum-silicon bonds.  
   
   
       4 . A complementary transistor pair on a semiconductor assembly comprising: 
 an NMOS transistor comprising hafnium-silicon bonds that create predominately Fermi level pinning near the valance band; and    a PMOS transistor comprising aluminum-silicon bonds that create predominately Fermi level pinning near the conductive band.    
   
   
       5 . A semiconductor memory device having a complementary transistor pair comprising: 
 an NMOS transistor comprising first metal-silicon bonds that create predominately Fermi level pinning near the valance band; and    a PMOS transistor comprising second metal-silicon bonds that create predominately Fermi level pinning near the conductive band.    
   
   
       6 . The complementary transistor pair of  claim 5 , wherein the first metal-silicon bonds comprise hafnium-silicon bonds.  
   
   
       7 . The complementary transistor pair of  claim 5 , wherein the second metal-silicon bonds comprise aluminum-silicon bonds.  
   
   
       8 . A semiconductor memory device having a complementary transistor pair comprising: 
 an NMOS transistor comprising hafnium-silicon bonds that create predominately Fermi level pinning near the valance band; and    a PMOS transistor comprising aluminum-silicon bonds that create predominately Fermi level pinning near the conductive band.    
   
   
       9 . A complementary transistor pair on a semiconductor assembly comprising: 
 a PMOS transistor comprising: 
 a PMOS transistor gate dielectric of silicon dioxide, a hafnium containing oxide and an aluminum oxide; and  
 a PMOS transistor gate comprising a silicon material directly overlying the aluminum oxide, the silicon material and the aluminum oxide forming aluminum-silicon bonds that create predominately Fermi level pinning near the valance band; and  
   an NMOS transistor comprising: 
 an NMOS transistor gate dielectric of the silicon dioxide and the hafnium containing oxide; and  
 an NMOS transistor gate comprising the silicon material directly overlying the hafnium containing oxide, the silicon material and the hafnium containing oxide forming hafnium-silicon bonds that create predominately Fermi level pinning near the conductive band.  
   
   
   
       10 . The complementary transistor pair of  claim 9 , wherein the hafnium containing oxide is HfO 2 .  
   
   
       11 . The complementary transistor pair of  claim 9 , wherein the hafnium containing oxide is HfSiO.  
   
   
       12 . The complementary transistor pair of  claim 9 , wherein the silicon material is polysilicon.  
   
   
       13 . The complementary transistor pair of  claim 9 , wherein the silicon dioxide is a nitrided silicon dioxide.  
   
   
       14 . A semiconductor memory device having a complementary transistor pair comprising: 
 a PMOS transistor comprising: 
 a PMOS transistor gate dielectric of silicon dioxide, a hafnium containing oxide and an aluminum oxide; and  
 a PMOS transistor gate comprising a silicon material directly overlying the aluminum oxide, the silicon material and the aluminum oxide forming aluminum-silicon bonds that create predominately Fermi level pinning near the valance band; and  
   an NMOS transistor comprising: 
 an NMOS transistor gate dielectric of the silicon dioxide and the hafnium containing oxide; and  
 an NMOS transistor gate comprising the silicon material directly overlying the hafnium containing oxide, the silicon material and the hafnium containing oxide forming hafnium-silicon bonds that create predominately Fermi level pinning near the conductive band.  
   
   
   
       15 . The complementary transistor pair of  claim 14 , wherein the hafnium containing oxide is HfO 2 .  
   
   
       16 . The complementary transistor pair of  claim 14 , wherein the hafnium containing oxide is HfSiO.  
   
   
       17 . The complementary transistor pair of  claim 14 , wherein the silicon material is polysilicon.  
   
   
       18 . The complementary transistor pair of  claim 14 , wherein the silicon dioxide is a nitrided silicon dioxide.