Metal oxide resistive memory and method of fabricating the same

Abstract

Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.

1 . A memory device comprising: 
 a substrate;    a lower conductive layer over the substrate;    an insulation layer covering the lower conductive layer and the substrate, including a first contact hole to expose at least a portion of the lower conductive layer;    a carbon nanotube formed in the first contact hole over the lower conductive layer;    a transition-metal oxide layer over the carbon nanotube; and    a top electrode over the transition-metal oxide layer.    
   
   
       2 . The memory device as set forth in  claim 1 , wherein the lower conductive layer includes a catalytic agent to help facilitate growth of the carbon nanotube.  
   
   
       3 . The memory device as set forth in  claim 2 , wherein the catalytic agent is chosen from Ni, Al, Co, Mo, Pt, Ca, Cr, Ti, Fe, Zr, W, Ir, Y, WSi, CoSi, NiSi, TiSi, and TiW.  
   
   
       4 . The memory device as set forth in  claim 1 , further comprising a bottom electrode interposed between the carbon nanotube and the transition-metal oxide layer.  
   
   
       5 . The memory device as set forth in  claim 4 , wherein a top surface of the bottom electrode is lower than a surface of the insulation layer.  
   
   
       6 . The memory device as set forth in  claim 4 , wherein the bottom electrode protrudes above a surface of the insulation layer.  
   
   
       7 . The memory device as set forth in  claim 4 , wherein the bottom electrode includes an oxygen diffusion-protecting layer.  
   
   
       8 . The memory device as set forth in  claim 1 , wherein the transition-metal oxide layer includes an oxide chosen from NiO, TiO 2 , ZrO 2 , HfO 2 , Nb 2 O 5 , CoO 2 , and CrO 2 .  
   
   
       9 . The memory device as set forth in  claim 8 , wherein the transition-metal oxide layer is doped with an element chosen from Li, Cr, Ca, and La.  
   
   
       10 . The memory device as set forth in  claim 1 , further comprising a metal silicide layer formed in the substrate.  
   
   
       11 . A memory device comprising: 
 a substrate including a silicide layer formed in the substrate;    a diffusion-protecting layer formed over the silicide layer;    a transition-metal oxide layer formed over the diffusion-protecting layer;    an insulation layer formed over the transition-metal oxide layer, the insulation layer having a contact hole exposing at least a portion of the transition-metal oxide layer;    a carbon nanotube formed in the contact hole over the transition-metal oxide layer; and    an upper conductive layer disposed over the insulation layer to overlap with the carbon nanotube.    
   
   
       12 . A memory device comprising: 
 a substrate;    a first insulation layer formed over the substrate;    a contact plug formed over the substrate and extending through the first insulation layer;    a lower conductive layer over the contact plug and at least a portion of the first insulation layer, the lower conductive layer including a transition-metal oxide layer;    a second insulation layer covering the lower conductive layer and the first insulation layer, the second insulation layer including a contact hole to expose at least a portion of the lower conductive layer;    a carbon nanotube formed in the contact hole over the lower conductive layer; and    an upper conductive layer over the insulation layer, the upper conductive layer overlying the carbon nanotube.    
   
   
       13 . The memory device as set forth in  claim 12 , wherein the lower conductive layer includes a bottom electrode, the transition-metal oxide layer formed over the bottom electrode, and a top electrode formed over the transition-metal oxide layer, where the top electrode includes a catalytic agent for growth of the carbon nanotube.  
   
   
       14 . The memory device as set forth in  claim 13 , wherein the bottom electrode includes a diffusion-protecting layer.  
   
   
       15 . The memory device as set forth in  claim 14 , wherein the diffusion-protecting layer is formed over an impurity region in the substrate.  
   
   
       16 . The memory device set forth in  claim 12 , further comprising a silicide layer formed in substrate, the silicide layer being in contact with the contact plug.  
   
   
       17 . The memory device set forth in  claim 16 , wherein the contact plug includes a second carbon nanotube.  
   
   
       18 . A method of fabricating a memory device, comprising: 
 forming a lower conductive layer on a substrate, the lower conductive layer including a catalytic agent for carbon nanotube growth;    growing a first carbon nanotube from the catalytic agent of the lower conductive layer, the first carbon nanotube grown to extend through at least a portion of a first insulation layer;    forming a transition-metal oxide layer that overlaps with the first carbon nanotube over the first insulation layer, where the transition-metal oxide layer is connected with the first carbon nanotube; and    forming a top electrode over the transition-metal-oxide layer.    
   
   
       19 . The method as set forth in  claim 18 , wherein the catalytic agent is formed by conducting an NH 3  plasma treatment over the lower conductive layer.  
   
   
       20 . The method as set forth in  claim 18 , wherein the catalytic agent is a catalytic metal layer deposited over the lower conductive layer.  
   
   
       21 . The method as set forth in  claim 20 , wherein the transition-metal oxide layer is generated by oxidation of the catalytic metal layer.  
   
   
       22 . The method as set forth in  claim 18 , wherein the growing the first carbon nanotube includes: 
 forming the first insulation layer over the lower conductive layer;    forming a first contact hole to expose at least a portion of the lower conductive layer; and    growing the first carbon nanotube in the contact hole over the lower conductive layer.    
   
   
       23 . The method as set forth in  claim 22 , further comprising forming a supporting insulation layer that fills a space between the first contact hole and the first carbon nanotube to surround the first carbon nanotube.  
   
   
       24 . The method as set forth in  claim 18 , wherein forming the first carbon nanotube and the first insulation layer includes: 
 growing the first carbon nanotube by the catalytic agent of the lower conductive layer along a vertical direction to the substrate; and    depositing the first insulation layer.    
   
   
       25 . The method as set forth in  claim 24 , further comprising etching the first insulation layer to expose an upward face of the first carbon nanotube.  
   
   
       26 . The method as set forth in  claim 18 , further comprising forming a bottom electrode that overlaps with the carbon nanotube over the insulation layer, wherein the transition-metal oxide layer is connected to the first carbon nanotube through the bottom electrode.  
   
   
       27 . The method as set forth in  claim 26 , wherein the bottom electrode includes an oxygen diffusion-protecting layer.  
   
   
       28 . The method as set forth in  claim 18 , further comprising: 
 forming an impurity diffusion region in a substrate; and    forming a metal silicide layer in the impurity diffusion region,    wherein the lower conductive layer includes the metal silicide layer.    
   
   
       29 . A method of fabricating a memory device comprising: 
 forming a silicide layer on a semiconductor substrate;    forming a diffusion-protecting layer over the silicide layer;    forming a transition-metal oxide layer over the diffusion-protecting layer;    forming an insulation layer over the substrate having the transition-metal oxide layer;    forming a contact hole in the insulation layer to expose at least a portion of the transition-metal oxide layer;    growing a carbon nanotube in the contact hole; and    forming an upper conductive layer over the insulation layer to overlap the carbon nanotube.    
   
   
       30 . A method of fabricating a metal oxide resistive memory device, comprising: 
 forming a first insulation layer on a substrate, the first insulation layer having a contact plug extending therethrough to contact the substrate;    forming a lower conductive layer including a transition-metal oxide layer over the contact plug and a portion of the first insulation layer;    growing a carbon nanotube over the lower conductive layer and forming a second insulation layer that surrounds the carbon nanotube; and    forming an upper conductive layer overlying the carbon nanotube and over the second insulation layer, where the upper conductive layer is electrically connected with the carbon nanotube.    
   
   
       31 . The method as set forth in  claim 30 , wherein forming the carbon nanotube and the second insulation layer includes: 
 forming the second insulation layer over the lower conductive layer;    forming a contact hole to expose at least a portion of the lower conductive layer; and    growing the carbon nanotube from the transition-metal oxide layer in the contact hole over the lower conductive layer, where the transition-metal oxide layer is used as a catalytic agent.    
   
   
       32 . The method as set forth in  claim 31 , further comprising forming a supporting insulation layer that fills a space between the contact hole and the carbon nanotube to surround the carbon nanotube.  
   
   
       33 . The method as set forth in  claim 30 , wherein forming the carbon nanotube and the second insulation layer includes: 
 growing the carbon nanotube by using the transition-metal oxide layer as a catalytic agent along a vertical direction to the substrate; and    depositing the second insulation layer.    
   
   
       34 . The method as set forth in  claim 33 , further comprising etching the second insulation layer to expose an upward face of the carbon nanotube.  
   
   
       35 . The method as set forth in  claim 30  further comprising forming a catalytic metal layer for the growth of the carbon nanotube over the transition-metal oxide layer.  
   
   
       36 . The method as set forth in  claim 30 , wherein forming the lower conductive electrode includes forming a top and a bottom electrode respectively on and under the transition-metal oxide layer.  
   
   
       37 . The method as set forth in  claim 36 , wherein forming the bottom electrode includes forming a diffusion-protecting layer.  
   
   
       38 . The method as set forth in  claim 30 , further comprising forming a silicide layer in the substrate before forming the first insulation layer, the first insulation layer being formed so that the contact plug is in contact with the silicide layer.  
   
   
       39 . The method as set forth in  claim 38 , wherein the contact plug in the insulation layer is a second carbon nanotube formed by growing the second carbon nanotube over the silicide layer to extend through the first insulation layer.