US2006261899A1PendingUtilityA1

Single-ended pseudo-differential output driver

Assignee: MICRON TECHNOLOGY INCPriority: Aug 31, 2004Filed: Jul 21, 2006Published: Nov 23, 2006
Est. expiryAug 31, 2024(expired)· nominal 20-yr term from priority
H03F 3/45179H03F 3/45183H03F 2203/45708
38
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A differential pair of transistors includes a first transistor and a second transistor having their sources coupled together. Their sources are further coupled to ground via a pull-down network. A single-ended output is coupled to the drain of the second of the pair of differential transistors. A differential current adjust circuit is coupled to a drain of the first of the pair of differential transistors, and the current adjust circuit is configured so that the second side of the differential output driver circuit conducts approximately the same current as the first side of the differential output driver circuit.

Claims

exact text as granted — not AI-modified
1 . A pseudo-differential driver circuit, comprising: 
 a differential pair of transistors, comprising a first transistor and a second transistor having their sources coupled together and further having their sources coupled to ground via a pull-down network;    a single-ended output coupled to the drain of the second of the pair of differential transistors; and    a differential current adjust circuit coupled to a drain of the first of the pair of differential transistors, the differential current adjust circuit configured so that the second side of the differential output driver circuit conducts approximately the same current as the first side of the differential output driver circuit.    
   
   
       2 . The pseudo-differential driver circuit of  claim 1 , wherein the pull-down network comprises a variable impedance, configurable to control the current flowing through the pull-down network.  
   
   
       3 . The pseudo-differential circuit of  claim 1 , wherein the drain of the first transistor is coupled to a supply voltage by one or more first resistors, and the drain of the second transistor is coupled to the supply voltage by one or more second resistors.  
   
   
       4 . The pseudo-differential circuit of  claim 3 , wherein: 
 the one or more first resistors are coupled to the supply voltage by one or more third transistors, the gate of the one or more fourth transistors coupled to a gate of the first transistor; and    the one or more second resistors are coupled to the supply voltage by one or more fourth transistors, the gate of the one or more fourth transistors coupled to a gate of the second transistor.    
   
   
       5 . A pseudo-differential output circuit, comprising: 
 a differential circuit;    a differential input comprising two differential signal lines of opposite polarity coupled to the differential circuit;    a single-ended pseudo-differential output comprising a single signal line; and    a differential current adjust circuit operable to control the current flowing through a leg of the differential circuit not coupled to the single-ended output.    
   
   
       6 . The pseudo-differential circuit of  claim 5 , wherein the pull-down network comprises one or more transistors, the one or more transistors operable to adjust the current flowing through the pull-down network and through the differential circuit.  
   
   
       7 . The pseudo-differential circuit of  claim 5 , wherein the differential current adjust circuit comprises at least one transistor coupling a supply voltage to a leg of the differential circuit opposite the leg coupled to the single-ended output.  
   
   
       8 . A method of operating a pseudo-differential driver circuit, comprising: 
 receiving a differential input signal in a differential circuit having a first leg and a second leg via first and second differential input transistors, the differential input signal comprising a first part and a second part that varies opposite the first part, such that the first part of the differential signal is received in the first differential input transistor in the first leg and the second part of the differential input signal is received in the second differential input transistor the second leg;    controlling current in a first leg of the differential circuit by varying the impedance between the differential signal input transistor in the first leg and a supply voltage; and    deriving a single-ended output from the second leg.    
   
   
       9 . The method of  claim 8 , further comprising controlling the current flowing through both legs of the differential circuit by coupling both legs of the differential circuit to a ground via a variable impedance pull-down circuit and varying the impedance of the variable impedance pull-down circuit.  
   
   
       10 . The method of  claim 9 , wherein coupling both legs of the differential circuit to ground via a variable impedance pull-down circuit comprises coupling both legs of the differential circuit to ground with the drain and source of a pull-down transistor, and wherein varying the impedance of the variable impedance pull-down circuit comprises altering the signal applied to a gate of the pull-down transistor.  
   
   
       11 . The method of  claim 8 , wherein varying the impedance between the first leg and a supply voltage comprises controlling the signal applied to the gate of a transistor coupling the first leg to the supply voltage.  
   
   
       12 . A method of operating an integrated circuit, comprising: 
 receiving a differential input signal in a differential circuit having a first leg and a second leg via first and second differential input transistors, the differential input signal comprising a first part and a second part that varies opposite the first part, such that the first part of the differential signal is received in the first differential input transistor in the first leg and the second part of the differential input signal is received in the second differential input transistor the second leg;    controlling current in a first leg of the differential circuit by varying the impedance between the differential signal input transistor in the first leg and a supply voltage; and    deriving a single-ended output from the second leg.    
   
   
       13 . The method of  claim 12 , further comprising controlling the current flowing through both legs of the differential circuit by coupling both legs of the differential circuit to a ground via a variable impedance pull-down circuit and varying the impedance of the variable impedance pull-down circuit.  
   
   
       14 . The method of  claim 13 , wherein coupling both legs of the differential circuit to ground via a variable impedance pull-down circuit comprises coupling both legs of the differential circuit to ground with the drain and source of a pull-down transistor, and wherein varying the impedance of the variable impedance pull-down circuit comprises altering the signal applied to a gate of the pull-down transistor.  
   
   
       15 . The method of  claim 13 , wherein varying the impedance between the first leg and a supply voltage comprises controlling the signal applied to the gate of a transistor coupling the first leg to the supply voltage.

Join the waitlist — get patent alerts

Track US2006261899A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.