US2006261484A1PendingUtilityA1

Electronic apparatus having polynorbornene foam insulation

Assignee: MICRON TECHNOLOGY INCPriority: Feb 22, 2000Filed: Jul 25, 2006Published: Nov 23, 2006
Est. expiryFeb 22, 2020(expired)· nominal 20-yr term from priority
Inventors:Paul A. Farrar
H10P 14/6538H10P 14/6536H10P 14/6342H10P 14/6334H10P 14/687H10P 14/665H10W 20/495H10W 74/137H10W 20/072H10W 20/48H10W 20/46H10P 14/683C08L 65/00H10B 10/00H10B 12/05
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Claims

Abstract

Various apparatus and systems include foamed polynorbornene insulating material. The foamed polynorbornene material may provide electrical insulation between conductive layers of an integrated circuit device.

Claims

exact text as granted — not AI-modified
1 . A memory comprising: 
 a first conductive layer;    a second conductive layer; and    a layer of foamed polynorbornene material electrically insulating the first conductive layer from the second conductive layer.    
   
   
       2 . The memory of  claim 1 , wherein the foamed polynorbornene material has a cell size of less than 1.0 micron.  
   
   
       3 . The memory of  claim 1 , wherein the second conductive layer includes one or more of aluminum, copper, gold, silver, tungsten, or alloys of combinations of aluminum, copper, gold, silver, tungsten.  
   
   
       4 . The memory of  claim 1 , wherein the first conductive layer includes an Al/Cu alloy, an Al/Cu/Si alloy, or a combination of an Al/Cu alloy and an Al/Cu/Si alloy.  
   
   
       5 . The memory of  claim 1 , wherein the first conductive layer couples to a first level of interconnection metal.  
   
   
       6 . The memory of  claim 1 , wherein a second layer of foamed polynorbornene material isolates the first conductive layer from an active area of a semiconductor device.  
   
   
       7 . A memory device comprising: 
 an array of memory cells;    a row access circuit coupled to the array of memory cells;    a column access circuit coupled to the array of memory cells;    an address decoder circuit coupled to the row access circuit and the column access circuit; and    two or more conductive layers coupled to one or more of the array of memory cells, the address decoder circuit, the row access circuit and the column access circuit, wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbornene material.    
   
   
       8 . The memory device of  claim 7 , wherein the foamed polynorbornene material includes a foamed polynorbornene material having approximately 0.1 to 0.2% weight loss per hour isothermal at approximately 300° C.  
   
   
       9 . The memory device of  claim 7 , wherein the foamed polynorbornene material has a cell size of less than about 3.0 microns.  
   
   
       10 . The memory device of  claim 7 , wherein the foamed polynorbornene material has a cell size of less than about 1.0 micron.  
   
   
       11 . The memory device of  claim 7 , wherein the foamed polynorbornene material has a cell size of less than about 0.1 microns.  
   
   
       12 . The memory device of  claim 11 , wherein the foamed polynorbornene material includes a foamed polynorbornene material having approximately 2-3% weight loss per hour isothermal at approximately 350° C.  
   
   
       13 . A memory module comprising: 
 a support;    a plurality of leads extending from the support;    a command link coupled to at least one of the plurality of leads;    a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and    a memory device contained on the support and coupled to the command link, the memory device including: 
 an array of memory cells;  
 a row access circuit coupled to the array of memory cells;  
 a column access circuit coupled to the array of memory cells;  
 an address decoder circuit coupled to the row access circuit and the column access circuit; and  
 two or more conductive layers coupled to one or more of the array of memory cells, the address decoder circuit, the row access circuit and the column access circuit, wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbornene material.  
   
   
   
       14 . The memory module of  claim 13 , wherein the foamed polynorbornene material has a cell size of less than about 3.0 microns.  
   
   
       15 . The memory module of  claim 13 , wherein the foamed polynorbornene material has a cell size of less than about 0.1 microns.  
   
   
       16 . The memory module of  claim 13 , wherein the foamed polynorbornene material includes a foamed polynorbornene material having approximately 2-3% weight loss per hour isothermal at approximately 350° C.  
   
   
       17 . A memory system comprising: 
 a controller;    a command link coupled to the controller;    a data link coupled to the controller; and    a memory device coupled to the command link and the data link, the memory device including: 
 an array of memory cells;  
 a row access circuit coupled to the array of memory cells;  
 a column access circuit coupled to the array of memory cells;  
 an address decoder circuit coupled to the row access circuit and the column access circuit; and  
 two or more conductive layers coupled to one or more of the array of memory cells, the address decoder circuit, the row access circuit and the column access circuit, wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbornene material.  
   
   
   
       18 . The memory system of  claim 17 , wherein the foamed polynorbornene material has a cell size of less than about 3.0 microns.  
   
   
       19 . The memory system of  claim 17 , wherein the foamed polynorbornene material has a cell size of less than about 0.1 microns.  
   
   
       20 . The memory system of  claim 17 , wherein the foamed polynorbornene material includes a foamed polynorbornene material having approximately 0.1 to 0.2% weight loss per hour isothermal at approximately 300° C.  
   
   
       21 . An electronic system comprising: 
 a processor; and    a circuit module having a plurality of leads coupled to the processor, the circuit module having a semiconductor die coupled to the plurality of leads, the semiconductor die including: 
 an integrated circuit supported by a substrate, the integrated circuit having a plurality of integrated circuit devices; and  
 two or more conductive layers coupled to the plurality of integrated circuit devices, wherein a first conductive layer of the two or more conductive layers is electrically insulated from a second conductive layer of the two or more conductive layers by a foamed polynorbornene material.  
   
   
   
       22 . The electronic system of  claim 21 , wherein the foamed polynorbornene material has a cell size of less than about 3.0 microns.  
   
   
       23 . The electronic system of  claim 21 , wherein the foamed polynorbornene material has a cell size of less than about 0.1 microns.  
   
   
       24 . The electronic system of  claim 21 , wherein the electronic system includes a computer.  
   
   
       25 . The electronic system of  claim 21 , wherein the electronic system includes a control system.

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