Integrated circuit device with treated perimeter edge

Abstract

An integrated circuit die and method of fabricating the same. The method comprises further grinding, polishing or otherwise treating one or more perimeter edges of an individual circuit die. The perimeter edges are treated to remove a substantial portion of the remaining substrate material layer or scribe therefrom without exposing the active circuitry of the die. The process reduces the overall length and width dimensions of a die producing a smaller circuit die without reducing the amount of circuitry on the die.

1 . An integrated circuit die cut from a wafer of substrate material, said die comprising: 
 an active surface having a circuit pattern formed thereon;    an inactive surface opposite said active surface;    at least one perimeter edge;    a layer of remaining substrate material on said at least one perimeter edge; and    wherein at least a portion of said layer of remaining substrate material is removed from said at least one perimeter edge of said integrated circuit die.    
   
   
       2 . The integrated circuit die of  claim 1 , further including a bi-level step on said at least one perimeter edge.  
   
   
       3 . The integrated circuit die of  claim 1 , further including a perimeter edge surface substantially perpendicular to at least one of the active and inactive surface and entirely contained within the remaining substrate material, the perimeter edge surface having a polished surface containing minimal defects and cut marks, and having at least one portion of the perimeter edge surface within five microns of at least one portion of the circuit pattern formed on the active surface.  
   
   
       4 . The integrated circuit die of  claim 1 , wherein said substrate includes at least one of single crystal silicon, polycrystalline silicon, amorphous silicon, epitaxial silicon, silicon on sapphire, silicon on insulator, germanium, silicon-germanium, gallium-arsenide, a III-V compound, silicon carbide, and diamond.  
   
   
       5 . A known good integrated circuit die cut from a wafer of substrate material to a first length and first width, said die comprising: 
 an active surface having a circuit pattern formed thereon;    an inactive surface opposite said active surface;    at least one perimeter edge;    a layer of remaining substrate material on said at least one perimeter edge; and    wherein at least a portion of said layer of remaining substrate material removed from said at least one perimeter edge of said integrated circuit die results in a second length and a second width less than the first length and first width.    
   
   
       6 . The known good integrated circuit die of  claim 5 , further including a perimeter edge surface substantially perpendicular to the active surface and entirely contained within the remaining substrate material, the perimeter edge surface having a polished smooth surface containing minimal defects and cut marks, and having at least one portion of the perimeter edge surface within five microns of at least one portion of the circuit pattern formed on the active surface.  
   
   
       7 . The known good integrated circuit die of  claim 6 , wherein said perimeter edge has a bi-level step with an upper portion of the perimeter having a portion within five microns of the circuit pattern, and a lower portion having a larger extent and being further horizontally and vertically from the circuit pattern.  
   
   
       8 . An integrated circuit assembly comprising a known good integrated circuit die cut from a wafer of substrate material and being mounted to a base, said die and said base encapsulated in a plastic material, wherein said known good integrated circuit die comprises: 
 an active surface having a circuit pattern formed thereon;    an inactive surface opposite said active surface;    at least one perimeter edge;    a layer of remaining substrate material on said at least one perimeter edge; and    wherein at least a portion of said layer of remaining substrate material is removed from said at least one perimeter edge of said integrated circuit die.    
   
   
       9 . The integrated circuit assembly of  claim 8 , further including a perimeter edge surface perpendicular to at least one of the active and inactive surface and entirely contained within the remaining substrate material, the perimeter edge surface having a polished smooth surface having at least one portion of the perimeter edge surface within five microns of at least one portion of the circuit pattern formed on the active surface.  
   
   
       10 . The integrated circuit assembly of  claim 9 , wherein said perimeter edge has a bi-level step with an upper portion of the perimeter having a portion within five microns of the circuit pattern, and a lower portion having a larger extent and being further horizontally and vertically from the circuit pattern.  
   
   
       11 . A semiconductor die, comprising: 
 a substrate that is one of cut and sawed from a semiconductor wafer, having a first planar surface having a first pair of orthogonal dimensions, having a first region with active circuitry thereon having a second pair of orthogonal dimensions smaller than the first pair, surrounded by an unused buffer area second region having a first width from an edge of the substrate to an edge of the first region;    a second planar surface opposite the first planar surface; and    one or more planar perimeter side surfaces disposed in the second region, each planar perimeter side surface extending continuously perpendicular from the first planar surface to the second planar surface.    
   
   
       12 . The semiconductor die of  claim 11 , wherein each planar perimeter side surface of the semiconductor die comprises a flat polished smooth surface with a top portion of each individual planar perimeter side surface disposed in the second region and having a first width of less than five microns from an edge of the first region to an edge of the substrate.  
   
   
       13 . The semiconductor die of  claim 11 , wherein the semiconductor die has a substantially rectangular shape.  
   
   
       14 . The semiconductor die of  claim 11 , wherein the second region is substantially crystal defect free, and the one or more planar perimeter side surfaces disposed in the second region are smooth as an unused portion of the top surface of the semiconductor wafer.  
   
   
       15 . A semiconductor die, comprising: 
 a planar surface having a first region with active circuitry thereon surrounded by an unused buffer area second region;    a plurality of perimeter side surfaces disposed in the second region, each having two portions extending perpendicular to the planar surface and having at least one portion disposed parallel to, but displaced vertically from the planar surface; and    a top portion of an upper one of the two perpendicular portions disposed within five microns of an edge of a portion of the active circuitry of the first region.    
   
   
       16 . The semiconductor die as recited in  claim 15 , wherein the semiconductor die comprises a shape having four substantially right angles.  
   
   
       17 . The semiconductor die as recited in  claim 15 , wherein a side surface of the upper one of the two perpendicular portions has a substantially flat surface with a smoothness equivalent to the surface smoothness of an unused portion of the top planar surface.  
   
   
       18 . A semiconductor die comprising: 
 a substrate having a substantially flat and smooth top planar surface having a first region with active circuitry thereon surrounded by a second region;    a substantially flat bottom planar surface opposite the first planar surface;    four perimeter sides disposed in the second region extending between the top planar surface and the bottom planar surface;    each perimeter side having two offset perimeter planar surfaces perpendicular to the top planar surface, where the two offset perimeter planar surfaces are substantially parallel to each other and offset in a horizontal direction from one another;    each perimeter side having a top one of the two offset perimeter planar surfaces extending from the top planar surface to an intermediate point, the bottom one of the two offset perimeter planar surfaces extending from the bottom planar surface to the intermediate point, and each of the offset perimeter planar surfaces is connected to the other by a third surface oriented in a horizontal direction at the intermediate point and parallel to the top planar surface.    
   
   
       19 . The semiconductor die as recited in  claim 18 , wherein a top edge portion of the top of the two offset perimeter planar surfaces is disposed in the second region within approximately 5 microns of an edge of the first region.  
   
   
       20 . The semiconductor die as recited in  claim 18 , wherein a top one of the two offset perimeter planar surfaces has a flat surface with a surface variation smoothness equivalent to the surface smoothness of an unused portion of the top planar surface.  
   
   
       21 . The semiconductor die as recited in  claim 18 , wherein both a top and a bottom one of the two offset perimeter planar surfaces has a flat surface with a surface variation smoothness equivalent to the surface smoothness of an unused portion of the top planar surface.