Methods for making nearly planar dielectric films in integrated circuits

Abstract

In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

1 . An integrated circuit, comprising: 
 one or more conductors;    a first insulative layer which is substantially free of voids and which contacts the one or more conductors;    a second insulative layer which lies of the first insulative layer and which includes a substantial number of voids.    
   
   
       2 . The integrated circuit of  claim 1 , wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.  
   
   
       3 . An integrated circuit, comprising: 
 one or more memory cells;    one or more conductors coupled to the one or more memory cells;    a first insulative layer which is substantially free of voids and which contacts the one or more conductors; and    a second insulative layer which lies on the first insulative layer and which includes a substantial number of voids.    
   
   
       4 . The integrated circuit of  claim 3 , wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.  
   
   
       5 . A system, comprising: 
 at least one integrated circuit, including a processor;    at least one integrated memory circuit operable coupled to the processor, comprising;    one or more memory cells;    one or more conductors coupled to the one or more memory cells;    a first insulative layer which is substantially free of voids and which contacts the one or more conductors;    a second insulative layer which lies on the first insulative layer and which includes a substantial number of voids.    
   
   
       6 . The system of  claim 5 , wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants.  
   
   
       7 . The system of  claim 5 , wherein the processor is a digital signal processor.  
   
   
       8 . An integrated circuit, comprising: 
 one or more conductors including an oxide spacer on one or more lateral sides of each of the conductors;    a first insulative layer having a first thickness disposed upon the one or more    conductors and formed at a first deposition rate to form voids in the first insulative layer; and    a second insulative layer having a second thickness disposed upon the first insulative layer and formed at a second deposition rate to form a substantially void free layer.    
   
   
       9 . The integrated circuit of  claim 8 , wherein the first and second insulative layers consist of silicon oxide and have different dielectric constants.  
   
   
       10 . The integrated circuit of  claim 8 , wherein the second deposition rate is less than the first deposition rate.  
   
   
       11 . The integrated circuit of  claim 8 , wherein the second insulative layer is facet etched to form sloping sides.  
   
   
       12 . The integrated circuit of  claim 8 , wherein the insulative layers include at least one via hole formed in the first and second insulative layers, and at least the second insulative layer is at least one of facet etched and thermally reflowed to form sloping sides of the at least one via hole.  
   
   
       13 . The integrated circuit of  claim 8 , wherein the one or more conductors further include a film resistant to lateral etching deposited upon the conductors.  
   
   
       14 . The integrated circuit of  claim 13 , wherein the film resistant to lateral etching is a TEOS, oxide-nitride film.  
   
   
       15 . An integrated circuit, comprising: 
 a first insulative layer having a first thickness and a first dielectric constant disposed upon one or more conductors and formed at a first deposition rate to form voids in the first insulative layer;    a second insulative layer having a second thickness and a second dielectric constant disposed upon the first insulative layer and formed at a second deposition rate that is less than the first deposition rate to form a substantially void free layer; and    the first and second insulative layers include at least one via hole formed in the first and second insulative layers, and at least the second insulative layer is at least one of facet etched and thermally reflowed to form sloping sides of the at least one via hole.    
   
   
       16 . The integrated circuit of  claim 15 , wherein the first and second insulative layers include at least one of silicon dioxide, silicon oxide, silicon rich oxide, a silicon oxynitride and a silicon nitride; and 
 wherein the one or more conductors include a dielectric spacer on one or more lateral sides of each of the conductors film that is resistant to lateral etching and formed of at least one of an oxide, an oxynitride, a nitride, a TEOS oxide, a TEOS oxynitride, a TEOS nitride, a spin-on dielectric, and a plasma oxide.    
   
   
       17 . An integrated circuit, comprising: 
 a plurality of conductors;    a first insulative layer having a first thickness disposed upon the plurality of conductors and formed at a first deposition rate to form voids in the first insulative layer;    a second insulative layer having a second thickness disposed upon the first insulative layer and formed at a second deposition rate to form a substantially void free layer;    wherein the plurality of conductors are disposed relative to one another to have a minimum separation and a maximum separation provided by individual ones of the plurality of conductors having a separation greater than the maximum separation, have at least one of a plurality of metal features inserted between the individual conductors, the feature selected from the list of pieces of metal including, a floating piece, a notch filling piece, a corner filling piece, and a between edges filling piece.    
   
   
       18 . The integrated circuit of  claim 17 , wherein the plurality of metal features have a width determined by a difference between the separation greater than the maximum separation of the individual ones of the plurality of conductors disposed relative to one another, and the minimum separation value to provide a separation approximately equal to the minimum separation.  
   
   
       19 . The integrated circuit of  claim 18 , wherein the plurality of metal features are selected by providing a first metal layout pattern having a first fill density; 
 generating a second metal layout pattern based upon the first metal layout pattern by identifying individual ones of the plurality of conductors having a separation greater than the maximum separation;    filling in one or more open areas of the first metal layout pattern having a separation greater than a predetermined value with floating metal;    filling in one or more notches in the first metal layout pattern having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;    filling in one or more corners of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;    filling in one or more opposing edges of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;    generating a second fill density for the second metal layout pattern and repeating the identifying the individual ones of the plurality of conductors having a separation greater than the maximum separation; and    continuing to generate metal layout patterns until at least one of a predetermined number of iterations occurs, and until none of the individual ones of the plurality of conductors has more than the maximum separation.    
   
   
       20 . An integrated circuit, comprising: 
 a plurality of conductors including an oxide spacer on one or more lateral sides of at least one of the conductors;    a first insulative layer having a first thickness disposed upon the plurality of conductors and formed at a first deposition rate to form voids in the first insulative layer;    a second insulative layer having a second thickness disposed upon the first insulative layer and formed at a second deposition rate to form a substantially void free layer;    wherein the plurality of conductors are disposed relative to one another to have a minimum separation and a maximum separation;    wherein the separation is determined by providing a first metal layout pattern having a first fill density;    generating a second metal layout pattern based upon the first metal layout pattern by identifying individual ones of the plurality of conductors having a separation greater than the maximum separation;    filling in one or more open areas of the first metal layout pattern having a separation greater than a predetermined value with floating metal;    filling in one or more notches in the first metal layout pattern having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;    filling in one or more corners of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;    filling in one or more opposing edges of the first metal layout having less than the predetermined value and more than the maximum value with added metal to at least one of the plurality of conductors;    generating a second fill density for the second metal layout pattern and repeating the identifying the individual ones of the plurality of conductors having a separation greater than the maximum separation; and    continuing to generate metal layout patterns until at least one of a predetermined number of iterations occurs, and until none of the individual ones of the plurality of conductors has more than the maximum separation.    
   
   
       21 . The integrated circuit of  claim 20 , wherein the first and second insulative layers consist essentially of silicon oxide and have substantially different dielectric constants, and the second deposition rate is less than the first deposition rate.  
   
   
       22 . The integrated circuit of  claim 20 , wherein the insulative layers include at least one via hole formed in the first and second insulative layers, and at least the second insulative layer is at least one of facet etched and thermally reflowed to form sloping sides of the at least one via hole.