US2006261421A1PendingUtilityA1

Boron incorporated diffusion barrier material

44
Individually held — no corporate assignee on recordPriority: Aug 24, 1999Filed: Jul 25, 2006Published: Nov 23, 2006
Est. expiryAug 24, 2019(expired)· nominal 20-yr term from priority
Inventors:Vishnu K. AgarwalGurtej S. Sandhu
H10D 64/01312H10W 20/032H10W 20/4441H10D 64/01318H10D 64/667H10D 64/664H10D 64/669
44
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Claims

Abstract

A diffusion barrier layer comprising TiN x B y is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiN x B y layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiN x B y layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

Claims

exact text as granted — not AI-modified
1 . An integrated circuit structure comprising: 
 an oxide;    a titanium boronitride barrier; and    a conductive material containing at least some fluorine atoms or ions;    wherein the titanium boronitride barrier is interposed between the oxide and the conductive material and inhibits diffusion of the fluorine atoms or ions from the conductive material into the oxide.    
   
   
       2 . The structure of  claim 1 , wherein the oxide comprises a gate oxide.  
   
   
       3 . The structure of  claim 1 , wherein the oxide has a thickness of about  30  angstroms to about 200 angstroms.  
   
   
       4 . The structure of  claim 1 , wherein the titanium boronitride barrier has a thickness of about 50 angstroms to about 500 angstroms.  
   
   
       5 . The structure of  claim 1 , wherein the conductive material comprises polysilicon.  
   
   
       6 . The structure of  claim 1 , wherein the conductive material comprises tungsten metal.  
   
   
       7 . The structure of  claim 1 , wherein the conductive material comprises tungsten silicide.  
   
   
       8 . The structure of  claim 1 , wherein the conductive material has a thickness of about 200 angstroms to about 4,000 angstroms.  
   
   
       9 . The structure of  claim 1 , further comprising a semiconductor substrate directly underlying the oxide.  
   
   
       10 . The structure of  claim 9 , wherein the semiconductor substrate comprises an intrinsically doped monocrystalline silicon wafer.  
   
   
       11 . The structure of  claim 9 , wherein the semiconductor substrate comprises an operable portion of a transistor array in a memory device.  
   
   
       12 . The structure of  claim 1 , wherein the titanium boronitride barrier comprises TiN x B y  wherein the x-factor is in the range of about 0.2 to about 0.499 and the y-factor is in the range of about 0.01 to about 10.  
   
   
       13 . The structure of  claim 12 , wherein the x-factor is in the range of about 0.25 to about 0.48 and the y-factor is in the range of about 0.1 to about 3.  
   
   
       14 . A memory device comprising: 
 an oxide;    a titanium boronitride barrier adjacent to at least a portion of the oxide;    a conductive material containing at least some fluorine atoms or ions; and    a polysilicon material interposed between the titanium boronitride barrier and the conductive material,    wherein the titanium boronitride barrier is interposed between the oxide and the polysilicon material and configured to inhibit diffusion of the fluorine atoms or ions from the conductive material into the oxide.    
   
   
       15 . The device of  claim 14 , wherein the oxide comprises a gate oxide.  
   
   
       16 . The device of  claim 14 , wherein the titanium boronitride barrier has a thickness of about 50 angstroms to about 500 angstroms.  
   
   
       17 . The device of  claim 14 , wherein the conductive material comprises tungsten.  
   
   
       18 . A method of forming an integrated circuit structure, the method comprising: 
 forming an oxide over a substrate;    forming a titanium boronitride barrier adjacent to at least a portion of the oxide; and    forming a conductive material adjacent to at least a portion of the titanium boronitride barrier, wherein forming the conductive material incorporates fluorine atoms or ions into the conductive material, and wherein the titanium boronitride barrier inhibits diffusion of the fluorine atoms or ions from the conductive material into the oxide.    
   
   
       19 . The method of  claim 18 , wherein the oxide comprises a gate oxide.  
   
   
       20 . The method of  claim 18 , wherein the oxide has a thickness of about 30 angstroms to about 200 angstroms.  
   
   
       21 . The method of  claim 18 , wherein the titanium boronitride barrier has a thickness of about 50 angstroms to about 500 angstroms.  
   
   
       22 . The method of  claim 18 , wherein forming the titanium boronitride barrier comprises: 
 forming a TiN layer; and    incorporating boron into the TiN layer.    
   
   
       23 . The method of  claim 22 , wherein incorporating boron into the TiN layer comprises exposing the TiN layer to a boron-containing gas in a chemical vapor deposition (CVD) chamber.  
   
   
       24 . The method of  claim 18 , wherein the titanium boronitride barrier is formed directly by chemical vapor deposition (CVD) using a titanium-containing source gas, a nitrogen-containing source gas, and a boron-containing source gas.  
   
   
       25 . The method of  claim 18 , wherein forming the titanium boronitride barrier comprises decomposing tetrakisdimethyl-aminotitanium (TDMAT) in the presence of a boron-containing source gas in a chemical vapor deposition (CVD) chamber.  
   
   
       26 . The method of  claim 18 , wherein forming the conductive material comprises combining a fluorine-containing metal source and a silicon source in a chemical vapor deposition (CVD) process.  
   
   
       27 . The method of  claim 26 , wherein the metal source comprises tungsten hexafluoride and wherein the silicon source comprises silicon tetrahydride.  
   
   
       28 . The method of  claim 18 , wherein forming the conductive material comprises: 
 depositing polysilicon; and    depositing a tungsten-containing material by chemical vapor deposition (CVD).    
   
   
       29 . The method of  claim 18 , wherein the conductive material has a thickness of about 200 angstroms to about 4,000 angstroms.  
   
   
       30 . The method of  claim 18 , wherein the substrate comprises an intrinsically doped monocrystalline silicon wafer.  
   
   
       31 . The method of  claim 18 , wherein the substrate comprises an operable portion of a transistor array in a memory device.

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