US2006261397A1PendingUtilityA1

Lanthanide oxide/hafnium oxide dielectric layers

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Assignee: MICRON TECHNOLOGY INCPriority: Jun 24, 2003Filed: Jul 26, 2006Published: Nov 23, 2006
Est. expiryJun 24, 2023(expired)· nominal 20-yr term from priority
Inventors:Kie Y. AhnLeonard Forbes
H10P 14/69397H10P 14/69396H10P 14/6339H10P 14/6332H10P 14/668H10P 14/662H10D 64/01346H10D 64/01342H10D 64/0134H10P 14/69392H10D 64/693H10D 64/035H10D 30/6759H10D 30/6739H10D 30/60H10D 1/684H10D 64/691H10D 64/685C23C 16/45525C23C 14/08C23C 16/405H10B 12/05H10B 12/03
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Claims

Abstract

Dielectric layers are provided configured with a layer of lanthanide oxide and a layer of hafnium oxide, where the layer of hafnium oxide is structured as one of more monolayers of hafnium oxide. In an embodiment, a dielectric layer may be arranged as a nanolaminate of hafnium oxide and a lanthanide oxide, with the layer of hafnium oxide structured as one of more monolayers of hafnium oxide.

Claims

exact text as granted — not AI-modified
1 . An electronic device comprising: 
 a first conductive region disposed on a substrate;    a dielectric layer disposed on the first conductive region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and    a first conductive region disposed on the dielectric layer, wherein the first conductive region, the dielectric layer, and the second conductive region are structured in a capacitor or in a transistor.    
   
   
       2 . The electronic device of  claim 1 , wherein the lanthanide oxide layer is disposed as an electron beam evaporated lanthanide oxide layer.  
   
   
       3 . The electronic device of  claim 1 , wherein the hafnium oxide layer and the lanthanide oxide layer are arranged as a hafnium oxide/lanthanide oxide nanolaminate.  
   
   
       4 . The electronic device of  claim 1 , wherein the lanthanide oxide layer has a thickness essentially between 2 nanometers and 10 nanometers.  
   
   
       5 . The electronic device of  claim 1 , wherein the lanthanide oxide layer includes Pr 2 O 3 .  
   
   
       6 . The electronic device of  claim 1 , wherein the dielectric layer includes Nd 2 O 3 .  
   
   
       7 . The electronic device of  claim 1 , wherein the dielectric layer includes Sm 2 O 3 .  
   
   
       8 . The electronic device of  claim 1 , wherein the dielectric layer includes Gd 2 O 3 .  
   
   
       9 . The electronic device of  claim 1 , wherein the dielectric layer includes Dy 2 O 3 .  
   
   
       10 . A capacitor, comprising: 
 a first conductive layer disposed on a substrate;    a dielectric layer disposed on the first conductive layer, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide, the hafnium oxide layer and lanthanide oxide layer disposed in a hafnium oxide/lanthanide oxide nanolaminate, the nanolaminate having one or more lanthanide oxide layers; and    a second conductive layer disposed on the dielectric layer, wherein the lanthanide layers of the nanolaminate have a combined thickness ranging from about 2 nanometers to about 10 nanometers.    
   
   
       11 . The capacitor of  claim 10 , wherein the lanthanide oxide layer includes an electronic beam evaporated lanthanide oxide layer.  
   
   
       12 . The capacitor of  claim 10 , wherein the hafnium oxide layer is disposed in contact with the first conductive layer.  
   
   
       13 . The capacitor of  claim 10 , wherein hafnium oxide/lanthanide oxide nanolaminate includes an electron beam evaporated lanthanide oxide layer disposed in contact with the first conductive layer.  
   
   
       14 . The capacitor of  claim 10 , wherein the lanthanide oxide layer includes one or more of Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , or Dy 2 O 3 .  
   
   
       15 . A transistor comprising: 
 a body region in a substrate between a source region and a drain region;    a dielectric layer disposed on the body region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and    a gate coupled to the dielectric layer.    
   
   
       16 . The transistor of  claim 15 , wherein the lanthanide oxide layer dielectric layer includes an electron beam evaporated lanthanide oxide layer.  
   
   
       17 . The transistor of  claim 15 , wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate.  
   
   
       18 . The transistor of  claim 15 , wherein the dielectric layer contains multiple electron beam evaporated lanthanide oxide layers with a combined thickness of the multiple electron beam evaporated lanthanide oxide layers ranging from about 2 nanometers and about 10 nanometers.  
   
   
       19 . The transistor of  claim 15 , wherein the dielectric layer contains multiple hafnium oxide layers, the hafnium oxide layers structured as one or more monolayers of hafnium oxide, the multiple hafnium oxide layers having a combined thickness of the multiple hafnium oxide layers ranging from about 2 nanometers and about 10 nanometers.  
   
   
       20 . The transistor of  claim 15 , wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate having multiple layers of lanthanide oxide, each layer of lanthanide oxide limited to a thickness of between about 2 nanometers and about 10 nanometers.  
   
   
       21 . The transistor of  claim 15 , wherein the lanthanide oxide layer includes a combination of lanthanide oxides, the oxides selected from the group of Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , and Dy 2 O 3 .  
   
   
       22 . A memory comprising: 
 a number of transistors, each transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a body region in a substrate between a source region and a drain region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and    a number of bit lines, each bit line coupled to one of the number of transistors.    
   
   
       23 . The memory of  claim 22 , wherein the dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate such that a combined thickness of the lanthanide oxide layers in the nanolaminate ranges from a thickness of 2 nanometers to 10 nanometers.  
   
   
       24 . The memory of  claim 22 , wherein the transistor is a transistor in a flash memory and the dielectric layer is an inter-gate dielectric of the transistor.  
   
   
       25 . The memory of  claim 22 , wherein the dielectric layer is structured as a nanolaminate.  
   
   
       26 . The memory of  claim 22 , wherein the dielectric layer includes a hafnium oxide/lanthanide oxide nanolaminate having a combined thickness of hafnium oxide layers ranging from about 2 nanometers to about 10 nanometers.  
   
   
       27 . The memory of  claim 22 , wherein the lanthanide oxide layer includes an electron beam evaporated lanthanide oxide layer having one or more Pr 2 O 3 , Nd 2 O 3 , Sm 2 O 3 , Gd 2 O 3 , or Dy 2 O 3 .  
   
   
       28 . An electronic system comprising: 
 a controller; and    an electronic device coupled to the controller, wherein at least one of the controller and the electronic device includes a dielectric layer, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide.    
   
   
       29 . The electronic system of  claim 28 , where the lanthanide oxide layer includes an electron beam evaporated lanthanide oxide layer.  
   
   
       30 . The electronic system of  claim 28 , wherein the hafnium oxide layer and the lanthanide oxide layer are layers in a lanthanide oxide/hafnium oxide nanolaminate.  
   
   
       31 . The electronic system of  claim 28 , wherein the dielectric layer contains multiple electron beam evaporated lanthanide oxide layers with a combined thickness of the multiple electron beam evaporated lanthanide oxide layers ranging from about 2 nanometers and about 10 nanometers.  
   
   
       32 . The electronic system of  claim 28 , wherein the dielectric layer contains multiple hafnium oxide layers with a combined thickness of the multiple hafnium oxide layers ranging from about 2 nanometers and about 10 nanometers.  
   
   
       33 . The electronic system of  claim 28 , wherein the lanthanide oxide layer includes Pr 2 O 3 .  
   
   
       34 . The electronic system of  claim 28 , wherein the lanthanide oxide layer includes one or more of Nd 2 O 3  or Sm 2 O 3 .  
   
   
       35 . The electronic system of  claim 28 , wherein the lanthanide oxide layer includes one or more of Gd 2 O 3  or Dy 2 O 3 .  
   
   
       36 . The electronic system of  claim 28 , wherein the electronic system includes an information handling device.  
   
   
       37 . The electronic system of  claim 28 , wherein the electronic system includes a wireless system.

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