Semiconductor device and method of manufacturing the same

Abstract

Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

1 . A semiconductor device comprising: 
 a semiconductor substrate;    first insulating film patterns formed on the semiconductor substrate;    a wiring formed on the first insulating film, the wiring including conductive film patterns and second insulating film patterns formed on the conductive film patterns;    third insulating film patterns formed on sidewalls of the wiring, the third insulating film patterns comprising a silicon-oxide-based material; and    contact patterns formed on the wiring, wherein the contact patterns include contact spacers formed on sidewalls thereof and define contact holes that pass through the first and third insulating film patterns.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the third insulating film patterns are continuously formed on surfaces and sidewalls of the wiring, and the contact patterns are formed on the third insulating film patterns positioned on the wiring.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the third insulating film patterns are self-aligned relative to the contact spacers.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the contact patterns are wider than the wiring.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the contact pattern and the contact spacer comprise materials having etching selectivities relative to the third insulating film pattern.  
   
   
       6 . The semiconductor device of  claim 5 , wherein the contact pattern and the contact spacer comprise silicon nitride or polysilicon.  
   
   
       7 . A semiconductor device comprising: 
 a semiconductor substrate having capacitor contact regions;    a first insulating film formed on the semiconductor substrate;    bit lines formed on the first insulating film between the capacitor contact regions, the bit lines including a conductive film pattern and an insulating film pattern formed on the conductive film pattern;    third insulating film patterns formed on sidewalls of the bit lines, the third insulating film including silicon oxide based material; and    contact patterns formed on the bit lines wherein the contact patterns include contact spacers formed on sidewalls thereof and define storage node contact holes that contact surfaces of the third insulating film patterns and pass through the first insulating film to expose the capacitor contact regions on the substrate between the bit lines.    
   
   
       8 . The semiconductor device of  claim 7 , wherein the capacitor contact region comprises a landing pad electrode.  
   
   
       9 . The semiconductor device of  claim 7 , wherein the third insulating film patterns are continuously formed on surfaces and sidewalls of the bit lines, and the contact patterns are formed on the third insulating film patterns positioned on the bit lines.  
   
   
       10 . The semiconductor device of  claim 7 , wherein the third insulating film patterns on the sidewalls of the bit lines are self-aligned relative to the contact spacers.  
   
   
       11 . The semiconductor device of  claim 7 , wherein the contact patterns are wider than the bit lines.  
   
   
       12 . The semiconductor device of  claim 7 , wherein the contact pattern and the contact spacer comprise materials having etching selectivities relative to the third insulating film pattern.  
   
   
       13 . The semiconductor device of  claim 12 , wherein the contact pattern and the contact spacer comprise silicon nitride or polysilicon.  
   
   
       14 . The semiconductor device of  claim 7 , further comprising storage node contact plugs formed in the storage node contact holes and connected to the capacitor contact regions wherein the storage node contact plugs are formed using a second conductive film.  
   
   
       15 . The semiconductor device of  claim 14 , wherein the storage node contact plugs are planarized when surfaces of the contact patterns are exposed.  
   
   
       16 . The semiconductor device of  claim 14 , wherein the third insulating film patterns are continuously formed on surfaces and sidewalls of the bit lines, and the storage node contact plugs are planarized until surfaces of the third insulating film patterns are exposed.  
   
   
       17 . A semiconductor device comprising, 
 a semiconductor substrate;    a first insulating film on the substrate;    conductive film patterns having sidewalls, and a second insulating film on the first insulating film; and    a third insulating film including a silicon-oxide-based material on sidewalls of the wiring, the third insulating film defining contact hole regions, the contact holes passing through the first insulating film,    whereby a parasitic capacitance between the wiring can be reduced because the silicon oxide on the sidewalls of the wiring has a low dielectric constant.    
   
   
       18 . A DRAM memory device including in combination: 
 a semiconductor substrate;    a plurality of bit-lines, the bit lines having silicon oxide spacers between the bit lines; and    gate electrodes for word lines, the gate electrodes including a gate insulating film, a gate capping film including silicon nitride and a gate sidewall spacer including silicon nitride.