Semiconductor circuit device and circuit simulation method for the same

Abstract

An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

1 - 15 . (canceled)  
   
   
       16 . A semiconductor circuit device comprising: 
 a first and second active areas provided in a first well of a first conductivity type in a semiconductor substrate, surrounded by a trench isolation and arranged in a channel length direction with the trench isolation therebetween;    a third and fourth active areas provided in a second well of a second conductivity type in the semiconductor substrate, surrounded by the trench isolation and arranged in a channel length direction with the trench isolation therebetween;    a first substrate active area of a first conductivity type arranged in a gate width direction of the first and second active areas with the trench isolation therebetween and on opposite side of the second well; and    a second substrate active area of a second conductivity type arranged in a gate width direction of the third and fourth active areas with the trench isolation therebetween and on opposite side of the first well,    wherein the first and second active areas are designed such that the ends of the first and second active areas, facing the third and fourth active areas, are aligned substantially on a single straight line.    
   
   
       17 . The semiconductor circuit device of  claim 16 , 
 wherein a length of the first active area in the gate width direction is equal to a length of the second active area in the gate width direction.    
   
   
       18 . The semiconductor circuit device of  claim 16 , 
 wherein a length of the first active area in the gate width direction is different from a length of the second active area in the gate width direction.    
   
   
       19 . The semiconductor circuit device of  claim 16 , 
 wherein a length of the first active area in a gate length direction is equal to a length of the second active area in a gate length direction.    
   
   
       20 . The semiconductor circuit device of  claim 16 , 
 wherein a length of the first active area in a gate length direction is different from a length of the second active area in a gate length direction.    
   
   
       21 . The semiconductor circuit device of  claim 16 , 
 wherein a length of the first active area in a gate length direction is equal to a length of the third active area in a gate length direction.    
   
   
       22 . The semiconductor circuit device of  claim 16 , 
 wherein a length of the first active area in a gate length direction is different from a length of the third active area in a gate length direction.    
   
   
       23 . The semiconductor circuit device of  claim 16 , 
 wherein a gate of at least one transistor is provided with each of the first and second active areas, and    at least one active area of the third and fourth active areas is a dummy active area in which a gate of a transistor is not provided.    
   
   
       24 . The semiconductor circuit device of  claim 16 , 
 wherein each of the third and fourth active areas is facing the first active area.    
   
   
       25 . The semiconductor circuit device of  claim 16 , 
 wherein the channel width of each transistor formed in the first and second active area is 1.0 μm or less.    
   
   
       26 . The semiconductor circuit device of  claim 16 , 
 wherein each of the first and second active areas is a PMIS active area provided with a gate of at least one P-channel transistor, and    each of the third and fourth active areas is a NMIS active area provided with a gate of at least one N-channel transistor.    
   
   
       27 . The semiconductor circuit device of  claim 16 , 
 wherein each of the first and second active areas is a NMIS active area provided with a gate of at least one N-channel transistor, and    each of the third and fourth active areas is a PMIS active area provided with a gate of at least one P-channel transistor.    
   
   
       28 . The semiconductor circuit device of  claim 16 , 
 wherein the first conductivity type is N-type, and    the second conductivity type is P-type.    
   
   
       29 . The semiconductor circuit device of  claim 16 , 
 wherein a distance between the end of the first active area facing the side of the second well and the first substrate active area and a distance between the end of the second active area facing the side of the second well and the first substrate active area are stable, and    a distance between the end of the third active area facing the side of the first well and the second substrate active area and a distance between the end of the fourth active area facing the side of the first well and the second substrate active area are stable.    
   
   
       30 . The semiconductor circuit device of  claim 16 , 
 wherein the third and fourth active areas are designed such that the ends of the third and fourth active areas, facing the first and second active areas, are aligned substantially on a single straight line.    
   
   
       31 . The semiconductor circuit device of  claim 16 , 
 wherein a distance between the first and third active areas in a gate width direction is substantially equal to a distance between the second and fourth active areas in a gate width direction.    
   
   
       32 . The semiconductor circuit device of  claim 16 , further comprising: 
 a fifth active area provided in the first well in the semiconductor substrate, surrounded by a trench isolation, aligned with the second active area in the channel length direction with the trench isolation therebetween; and    a sixth active area provided in the second well in the semiconductor substrate, surrounded by a trench isolation, aligned with the fourth active area in the channel length direction with the trench isolation therebetween,    wherein the fifth active area is designed such that the end of the fifth active area, facing the sixth active area, is aligned substantially on a single straight line.    
   
   
       33 . A semiconductor circuit device comprising: 
 a first and second active areas provided in a first well of a first conductivity type in a semiconductor substrate, surrounded by a trench isolation and arranged in a channel length direction with the trench isolation therebetween; and    a third and fourth active areas provided in a second well of a second conductivity type in the semiconductor substrate, surrounded by the trench isolation and arranged in a channel length direction with the trench isolation therebetween,    wherein the first and second active areas are facing the third and fourth active areas in a channel width direction and a distance therebetween is 0.8 μm or less, and    the first and second active areas are designed such that the ends of the first and second active areas, facing the third and fourth active areas, are aligned substantially on a single straight line.    
   
   
       34 . The semiconductor circuit device of  claim 33 , 
 wherein a length of the first active area in a gate width direction is equal to a length of the second active area in a gate width direction.    
   
   
       35 . The semiconductor circuit device of  claim 33 , 
 wherein a length of the first active area in a gate width direction is different from a length of the second active area in a gate width direction.    
   
   
       36 . The semiconductor circuit device of  claim 33 , 
 wherein a length of the first active area in a gate length direction is equal to a length of the second active area in a gate length direction.    
   
   
       37 . The semiconductor circuit device of  claim 33 , 
 wherein a length of the first active area in a gate length direction is different from a length of the second active area in a gate length direction.    
   
   
       38 . The semiconductor circuit device of  claim 33 , 
 wherein a length of the first active area in a gate length direction is equal to a length of the third active area in a gate length direction.    
   
   
       39 . The semiconductor circuit device of  claim 33 , 
 wherein a length of the first active area in a gate length direction is different from a length of the third active area in a gate length direction.    
   
   
       40 . The semiconductor circuit device of  claim 33 , 
 wherein a gate of at least one transistor is provided with the first and second active areas, and    at least one active area of the third and fourth active areas is a dummy active area in which a gate of a transistor is not provided.    
   
   
       41 . The semiconductor circuit device of  claim 33 , 
 wherein each of the third and fourth active areas is facing the first active area.    
   
   
       42 . The semiconductor circuit device of  claim 33 , 
 wherein the channel width of each transistor formed in the first and second active area is 1.0 μm or less.    
   
   
       43 . The semiconductor circuit device of  claim 33 , 
 wherein each of the first and second active area is a PMIS active area provided with a gate of at least one P-channel transistor, and    each of the third and fourth active area is a NMIS active area provided with a gate of at least one N-channel transistor.    
   
   
       44 . The semiconductor circuit device of  claim 33 , 
 wherein each of the first and second active area is a NMIS active area provided with a gate of at least one N-channel transistor, and    each of the third and fourth active area is a PMIS active area provided with a gate of at least one P-channel transistor.    
   
   
       45 . The semiconductor circuit device of  claim 33 , 
 wherein the third and fourth active areas are designed such that the ends of the third and fourth active areas, facing the first and second active areas, are aligned substantially on a single straight line.    
   
   
       46 . The semiconductor circuit device of  claim 33 , 
 wherein a distance between the first and third active areas in the gate width direction is substantially equal to a distance between the second and fourth active areas in a gate width direction.