Logic and memory device integration

Abstract

Memory devices are adapted for direct interface or virtual integration with a processor or other logic device through a local bus and isolated from a system bus. Such memory devices are capable of lower power requirements and reduced size due in part to the elimination of certain redundant circuitry. Direct interfacing through the local bus facilitates the elimination or reduction of input/output (I/O) buffer circuitry by eliminating the need to step up to and step down from typical system bus voltage levels. Communication between the memory device and a separate logic device occurs across the local bus at voltage levels compatible with internal logic levels of the memory device.

1 . A memory device, comprising: 
 a memory array; and    at least one nominally-buffered signal line, substantially incapable of level translation, for communication between the memory array and an external device;    wherein the memory device is devoid of logic functions capable of command interpretation; and    wherein the memory device is devoid of logic functions capable of address decoding.    
   
   
       2 . The memory device of  claim 1 , wherein the at least one nominally-buffered signal line comprises: 
 at least one control signal line for receiving control signals from the external device;    at least one address signal line for receiving address signals from the external device for accessing a portion of the memory array in response to the control signals; and    at least one data signal line for receiving data signals from the external device for writing to the accessed portion of the memory array.    
   
   
       3 . The memory device of  claim 1 , wherein the at least one nominally-buffered signal line is a non-buffered signal line.  
   
   
       4 . The memory device of  claim 1 , wherein the at least one nominally-buffered signal line is multiplexed to service more than one signal.  
   
   
       5 . The memory device of  claim 1 , wherein the at least one nominally-buffered signal line comprises: 
 a plurality of nominally-buffered data signal lines;    a plurality of nominally-buffered address signal lines; and    a plurality of nominally-buffered control signal lines.    
   
   
       6 . The memory device of  claim 1 , wherein the at least one nominally-buffered signal line is a data signal line.  
   
   
       7 . The memory device of  claim 1 , wherein the at least one nominally-buffered signal line is an address signal line.  
   
   
       8 . The memory device of  claim 1 , wherein the at least one nominally-buffered signal line is a control signal line.  
   
   
       9 . A memory device, comprising: 
 a memory array; and    at least one control signal line for receiving decoded control signals from an external device to control operations on the memory array;    at least one address signal line for receiving decoded address signals from the external device;    wherein the memory device is devoid of logic functions capable of command interpretation; and    wherein the memory device is devoid of logic functions capable of address decoding.    
   
   
       10 . The memory device of  claim 9 , wherein each address signal line is a nominally-buffered signal line.  
   
   
       11 . The memory device of  claim 9 , wherein the at least one address signal line is a non-buffered signal line.  
   
   
       12 . The memory device of  claim 9 , wherein each control signal line is a nominally-buffered signal line.  
   
   
       13 . The memory device of  claim 9 , wherein the at least one control signal line is a non-buffered signal line.  
   
   
       14 . A memory device, comprising: 
 a memory array; and    at least one control signal line for receiving decoded control signals from an external device to control operations on the memory array;    at least one address signal line for receiving decoded address signals from the external device;    wherein the memory device is devoid of logic functions capable of command interpretation;    wherein the memory device is devoid of logic functions capable of address decoding; and    wherein each control signal line and address signal line is substantially incapable of level translation.    
   
   
       15 . A memory device, comprising: 
 a memory array;    at least one control signal line for receiving control signals from an external device;    at least one address signal line for receiving address signals from the external device for accessing a portion of the memory array in response to the control signals; and    at least one data signal line for communicating data signals between the external device and an accessed portion of the memory array;    wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation;    wherein the memory device is devoid of logic functions capable of command interpretation; and    wherein the memory device is devoid of logic functions capable of address decoding.    
   
   
       16 . A memory device, comprising: 
 a memory array;    at least one control signal line for receiving control signals from an external device;    at least one address signal line for receiving address signals from the external device for accessing a portion of the memory array in response to the control signals; and    at least one data signal line for communicating data signals between the external device and an accessed portion of the memory array;    wherein at least one control signal line, address signal line or data signal line is adapted for use with voltage levels that are compatible with internal logic levels of the memory array;    wherein at least one control signal line, address signal line or data signal line is a nominally-buffered signal line;    wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation;    wherein the memory device is devoid of logic functions capable of command interpretation; and    wherein the memory device is devoid of logic functions capable of address decoding.    
   
   
       17 . An electronic system, comprising: 
 a logic device for coupling to a system bus;    a memory device separate from the logic device; and    a local bus coupled between the logic device and the memory device;    wherein the memory device comprises at least one nominally-buffered signal line coupled to the local bus; and    wherein the at least one nominally-buffered signal line is multiplexed to service more than one signal.    
   
   
       18 . The electronic system of  claim 17 , wherein the at least one nominally-buffered signal line is a non-buffered signal line.  
   
   
       19 . The electronic system of  claim 17 , wherein the at least one nominally-buffered signal line is substantially incapable of level translation.  
   
   
       20 . An electronic system, comprising: 
 a logic device for coupling to a system bus;    a memory device separate from the logic device; and    a local bus coupled between the logic device and the memory device;    wherein the memory device includes at least one nominally-buffered signal line coupled to the local bus;    wherein the memory device is devoid of logic functions capable of command interpretation;    wherein the memory device is devoid of logic functions capable of address decoding; and    wherein the at least one nominally-buffered signal line comprises: 
 a plurality of nominally-buffered data signal lines;  
 a plurality of nominally-buffered address signal lines; and  
 a plurality of nominally-buffered control signal lines.  
   
   
   
       21 . An electronic system, comprising: 
 a logic device for coupling to a system bus;    a memory device separate from the logic device; and    a local bus coupled between the logic device and the memory device;    wherein the memory device includes at least one nominally-buffered signal line coupled to the local bus;    wherein the memory device is devoid of logic functions capable of command interpretation;    wherein the memory device is devoid of logic functions capable of address decoding; and    wherein the memory device comprises a memory array and the at least one nominally-buffered signal line comprises: 
 at least one control signal line for receiving control signals from the logic device;  
 at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and  
 at least one data signal line for receiving data signals from the logic device for writing to the accessed portion of the memory array.  
   
   
   
       22 . An electronic system, comprising: 
 a logic device for coupling to a system bus;    a memory device separate from the logic device; and    a local bus coupled between the logic device and the memory device;    wherein the memory device comprises: 
 at least one control signal line for receiving control signals from the logic device;  
 at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and  
 at least one data signal line for receiving data signals from the logic device for writing to the accessed portion of the memory array;  
   wherein the memory device is devoid of logic functions capable of command interpretation;    wherein the memory device is devoid of logic functions capable of address decoding; and    wherein each control signal line, address signal line, and data signal line is substantially incapable of level translation.    
   
   
       23 . An electronic system, comprising: 
 a logic device for coupling to a system bus;    a memory device separate from the logic device; and    a local bus coupled between the logic device and the memory device;    wherein the memory device comprises: 
 a memory array;  
 at least one control signal line for receiving control signals from the logic device;  
 at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and  
 at least one data signal line for communicating data signals between the logic device and an accessed portion of the memory array;  
 wherein at least one control signal line, address signal line or data signal line is adapted for use with voltage levels that are compatible with internal logic levels of the memory array; and  
 wherein at least one control signal line, address signal line or data signal line is a nominally-buffered signal line.  
   
   
   
       24 . The electronic system of  claim 23 , wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation.  
   
   
       25 . The electronic system of  claim 23 , wherein the memory device is devoid of logic functions capable of command interpretation.  
   
   
       26 . The electronic system of  claim 23 , wherein the memory device is devoid of logic functions capable of address decoding.  
   
   
       27 . An electronic system, comprising: 
 a logic device for coupling to a system bus;    a memory device separate from the logic device; and    a local bus coupled between the logic device and the memory device;    wherein the memory device comprises: 
 a memory array;  
 at least one control signal line for receiving control signals from the logic device;  
 at least one address signal line for receiving address signals from the logic device for accessing a portion of the memory array in response to the control signals; and  
 at least one data signal line for communicating data signals between the logic device and an accessed portion of the memory array;  
 wherein at least one control signal line, address signal line or data signal line is adapted for use with voltage levels that are compatible with internal logic levels of the memory array;  
 wherein at least one control signal line, address signal line or data signal line is a nominally-buffered signal line;  
 wherein at least one control signal line, address signal line or data signal line is substantially incapable of level translation;  
 wherein the memory device is devoid of logic functions capable of command interpretation; and  
 wherein the memory device is devoid of logic functions capable of address decoding.