Capacitor structure

Abstract

A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as opposed to a depositing a single thick layer. Further, at least one of the oxidation steps is less aggressive than the oxidation environment or environments that would be used to deposit the single thick layer. This allows greater control over oxidizing the dielectric and other components beyond the dielectric.

1 . A metal-insulator-silicon device, comprising: 
 a top metal electrode;    a top tantalum pentoxide (Ta 2 O 5 ) layer under the top metal electrode;    a bottom tantalum pentoxide (Ta 2 O 5 ) layer under the top tantalum pentoxide (Ta 2 O 5 ) layer and contacting the top tantalum pentoxide (Ta 2 O 5 ) layer;    a silicon nitride layer under the bottom tantalum pentoxide (Ta 2 O 5 )layer; and    a bottom silicon electrode under the silicon nitride layer.    
   
   
       2 . The device of  claim 1 , wherein the top metal electrode is comprised of at least one of copper, aluminum, platinum, palladium, rhodium, gold, iridium and silver.  
   
   
       3 . The device of  claim 1 , wherein the top tantalum pentoxide (Ta 2 O 5 ) layer includes a thickness that ranges between approximately 10 Angstroms and approximately 40 Angstroms.  
   
   
       4 . The device of  claim 1 , wherein the top tantalum pentoxide (Ta 2 O 5 ) layer includes a thickness of at least about 20 Angstroms.  
   
   
       5 . The device of  claim 1 , further comprising a dielectric thickness that includes respective thicknesses of the top tantalum pentoxide (Ta 2 O 5 ) layer, the bottom tantalum pentoxide (Ta 2 O 5 ) layer and the silicon nitride layer, further wherein the thickness of the top tantalum pentoxide (Ta 2 O 5 ) layer ranges between approximately 14% and approximately 80% of the dielectric thickness.  
   
   
       6 . The device of  claim 1 , wherein the bottom silicon electrode is comprised of a hemispherical grain-silicon that further includes phosphorous.  
   
   
       7 . The device of  claim 1 , wherein the top metal electrode comprises a first electrode of a capacitor structure and the bottom silicon electrode comprises an opposing second electrode structure of the capacitor structure, and further wherein the top tantalum pentoxide (Ta 2 O 5 ) layer, the bottom tantalum pentoxide (Ta 2 O 5 ) layer and the silicon nitride layer comprise a dielectric structure positioned between the first electrode structure and the second electrode structure.  
   
   
       8 . The device of  claim 7 , wherein the capacitor structure further comprises a portion of a memory cell in a dynamic random access memory device.  
   
   
       9 . A capacitor structure for a semiconductor device, comprising: 
 a first electrode structure;    a second electrode structure spaced apart from the first electrode structure; and    a dielectric structure interposed between the first electrode structure and the second electrode structure, the dielectric structure further comprising at least two layers of a dielectric material.    
   
   
       10 . The capacitor structure of  claim 9 , wherein the first electrode structure is comprised of one of an acceptor-doped and a donor-doped semiconductor material.  
   
   
       11 . The capacitor structure of  claim 9 , wherein the first electrode structure is comprised of at least one of copper, aluminum, platinum, palladium, rhodium, gold, iridium, silver, titanium nitride, tin nitride, ruthenium nitride, zirconium nitride, ruthenium dioxide, tin oxide and titanium monoxide.  
   
   
       12 . The capacitor structure of  claim 9 , wherein the second electrode structure is comprised of one of an acceptor-doped and a donor-doped semiconductor material.  
   
   
       13 . The capacitor structure of  claim 9 , wherein the second electrode structure is comprised of at least one of copper, aluminum, platinum, palladium, rhodium, gold, iridium, silver, titanium nitride, tin nitride, ruthenium nitride, zirconium nitride, ruthenium dioxide, tin oxide and titanium monoxide.  
   
   
       14 . The capacitor structure of  claim 9 , wherein at least one of the dielectric layers is comprised of barium strontium titanate (BST).  
   
   
       15 . The capacitor structure of  claim 14 , wherein the barium strontium titanate (BST) layer includes a thickness that ranges between approximately 20 Angstroms and approximately 80 Angstroms.  
   
   
       16 . The capacitor structure of  claim 14 , further comprising a thickness of the dielectric structure, wherein one of the at least two layers of a dielectric material includes a barium strontium titanate (BST) layer having a thickness that ranges between approximately 10% and approximately 40% of the thickness of the dielectric structure.  
   
   
       17 . The capacitor structure of  claim 9 , wherein at least one of the dielectric layers is comprised of tantalum pentoxide (Ta 2 O 5 ).  
   
   
       18 . The capacitor structure of  claim 9 , wherein at least one of the dielectric layers is comprised of silicon nitride.  
   
   
       19 . The capacitor structure of  claim 9 , wherein one of the at least two layers of a dielectric material includes a tantalum pentoxide layer having a thickness that ranges between approximately 10 Angstroms and approximately 40 Angstroms.  
   
   
       20 . The capacitor structure of  claim 9 , wherein one of the at least two layers of a dielectric material includes a tantalum pentoxide (Ta 2 O 5 ) layer having a thickness of at least about 20 Angstroms.  
   
   
       21 . The capacitor structure of  claim 9 , further comprising a thickness of the dielectric structure, wherein one of the at least two layers of a dielectric material includes a tantalum pentoxide (Ta 2 O 5 ) layer having a thickness that ranges between approximately 14% and approximately 80% of the thickness of the dielectric structure.  
   
   
       22 . The capacitor structure of  claim 9 , wherein at least one of the first electrode and the second electrode is comprised of a hemispherical grain-silicon that further includes phosphorous.