Ultra high density flash memory

Abstract

An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for four vertical floating gate transistors that have individual floating and control gates distributed on the four sides of the pillar. Mutually orthogonal first gate lines and second gate lines provide addressing of the control gates. First source/drain terminals are row addressable by interconnection lines disposed substantially parallel to the first gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the second gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F 2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F 2 is needed per bit of data.

1 . A method of forming a memory array on a substrate, comprising: 
 forming a first source/drain layer at a surface of the substrate;    forming a semiconductor epitaxial layer on the first source/drain layer;    forming a second source/drain layer at a surface of the epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming a first gate dielectric layer substantially adjacent to sidewall regions of the first troughs;    forming a first conductive layer in the first troughs;    removing a portion of the first conductive layer in the first troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the first gate dielectric layer;    etching a portion of the substrate underlying a portion of the first troughs between the floating gate regions;    forming a first intergate dielectric layer on exposed portions of the floating gate regions in the first troughs;    forming first gate lines in the underlying etched portion of the substrate between opposing floating gate regions in the first troughs; and    forming control gate regions in the first troughs between opposing floating gate regions and separated therefrom by the first intergate dielectric layer.    
   
   
       2 . The method of  claim 1 , further comprising: 
 etching, in a second direction that is substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    forming a second gate dielectric layer substantially adjacent to sidewall regions of the second troughs;    forming a second conductive layer in the second troughs;    removing a portion of the second conductive layer in the second troughs such that floating gate regions are formed along the sidewall regions therein and separated from the sidewall regions by the second gate dielectric layer;    forming a second intergate dielectric layer on exposed portions of the floating gate regions in the second troughs; and    forming control gate regions and second gate lines between opposing floating gate regions in the second troughs by the second intergate dielectric layer.    
   
   
       3 . The method of  claim 1 , wherein the substrate further comprises a bulk semiconductor.  
   
   
       4 . The method of  claim 1 , wherein the substrate further comprises a semiconductor on insulator portion.  
   
   
       5 . The method of  claim 1 , further comprising: 
 forming an insulating layer undercutting semiconductor regions between the first troughs.    
   
   
       6 . The method of  claim 2 , further comprising: 
 forming a thin silicon nitride oxidation barrier layer by chemical vapor deposition on the sidewall regions of the second troughs;    anisotropically etching the thin silicon nitride oxidation barrier layer to expose bottom portions of the second troughs;    forming a bottom insulation layer on the bottom portions of the second troughs by thermal oxidation; and    stripping the thin silicon nitride oxidation barrier layer from the sidewall regions of the second troughs by a brief phosphoric acid etch.    
   
   
       7 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer and comprising P-silicon;    forming a thin layer of silicon dioxide on the second source/drain layer;    forming a layer of silicon nitride on the thin layer of silicon dioxide;    etching a plurality of substantially parallel troughs in the epitaxial layer;    forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    forming gate lines between opposing floating gate regions in the troughs; and    forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       8 . The method of  claim 7 , wherein forming the first source/drain layer further comprises forming the first source/drain layer with an approximate thickness ranging between 0.2 microns and 0.5 microns.  
   
   
       9 . The method of  claim 7 , wherein forming the thin layer of silicon dioxide further comprises forming the thin layer of silicon dioxide with an approximate thickness of 10 nanometers.  
   
   
       10 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate, the first source/drain comprising N+ silicon formed by epitaxial growth of silicon upon the substrate;    forming a semiconductor epitaxial layer on the first source/drain layer;    forming a second source/drain layer at a surface of the epitaxial layer by ion implantation, the second source/drain layer comprising N+ silicon and having an approximate thickness of 150 nanometers;    forming a thin layer of silicon dioxide on the second source/drain layer, the thin layer of silicon dioxide having an approximate thickness of 10 nanometers;    forming a layer of silicon nitride on the thin layer of silicon dioxide, the layer of silicon nitride having an approximate thickness of 200 nanometers;    etching a plurality of substantially parallel troughs in the epitaxial layer;    forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    forming gate lines between opposing floating gate regions in the troughs; and    forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       11 . The method of  claim 10 , wherein forming the first source/drain layer further comprises forming the first source/drain layer with an approximate thickness ranging between 0.2 microns and 0.5 microns.  
   
   
       12 . The method of  claim 10 , wherein forming at least two floating gate regions further comprises forming the at least two floating gate regions along the sidewall regions of the troughs and separated from the sidewall regions by the gate dielectric layer, the gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.  
   
   
       13 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate, the substrate comprised of a semiconductor-on-insulator portion, and the a first source/drain layer comprising N+ silicon formed by ion implantation of donor dopants into the substrate;    forming a semiconductor epitaxial layer on the first source/drain layer, the semiconductor epitaxial layer comprising P-silicon and having an approximate thickness of 0.6 microns;    forming a second source/drain layer at a surface of the epitaxial layer by ion implantation, the second source/drain layer comprising N+silicon and having an approximate thickness of 150 nanometers;    forming a thin layer of silicon dioxide on the second source/drain layer;    forming a layer of silicon nitride on the thin layer of silicon dioxide;    etching a plurality of substantially parallel troughs in the epitaxial layer;    forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    forming gate lines between opposing floating gate regions in the troughs; and    forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       14 . The method of  claim 13 , further comprising: 
 forming a conductive layer in the troughs.    
   
   
       15 . The method of  claim 14 , further comprising: 
 removing a portion of the conductive layer in the troughs; and    etching a portion of the substrate underlying a portion of the troughs between floating gate regions.    
   
   
       16 . The method, comprising: 
 forming a first source/drain layer at a surface of a substrate, the first source/drain comprising N+silicon formed by ion implantation of donor dopants into the substrate;    forming a second source/drain layer at a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer and comprising P-silicon;    forming a thin layer of silicon dioxide on the second source/drain layer;    forming a layer of silicon nitride on the thin layer of silicon dioxide;    etching a plurality of substantially parallel troughs in the epitaxial layer;    forming an insulating layer undercutting semiconductor regions between the troughs;    forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    forming gate lines between opposing floating gate regions in the troughs; and    forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       17 . The method of  claim 16 , wherein forming at least two floating gate regions further comprises forming at least two floating gate regions along the sidewall regions of the troughs and separated from the sidewall regions by the gate dielectric layer, the gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.  
   
   
       18 . The method of  claim 16 , wherein forming control gate regions further comprises forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer, the intergate dielectric layer having an approximate thickness that ranges between 7 nanometers and 15 nanometers.  
   
   
       19 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer;    etching a plurality of substantially parallel troughs in the epitaxial layer;    forming a thin silicon nitride oxidation barrier layer by chemical vapor deposition on sidewall regions of the troughs;    anisotropically etching the thin silicon nitride oxidation barrier layer to expose bottom portions of the troughs;    forming a bottom insulation layer on the bottom portions of the troughs by thermal oxidation;    forming at least two floating gate regions along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer; and    forming control gate regions in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       20 . The method of  claim 19 , further comprising: 
 planarizing the first conductive layer using a chemical mechanical polish.    
   
   
       21 . The method of  claim 19 , further comprising: 
 stripping the thin silicon nitride oxidation barrier layer from the sidewall regions by a phosphoric acid etch.    
   
   
       22 . The method of  claim 19 , wherein forming a first source/drain layer further comprises: 
 forming the first source/drain layer at the surface of the substrate, wherein the substrate is a bulk semiconductor.    
   
   
       23 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming a first bottom insulation layer on bottom portions of the first troughs by thermal oxidation;    forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    forming second control gate regions in the troughs between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.    
   
   
       24 . The method of  claim 23 , further comprising: 
 forming a second bottom insulation layer on bottom portions of the second troughs by thermal oxidation.    
   
   
       25 . The method of  claim 23 , further comprising: 
 forming the second dielectric layer by deposition of oxynitride using chemical vapor deposition.    
   
   
       26 . The method of  claim 23 , wherein forming first floating gate regions further comprises: 
 forming the first floating gate regions along the sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.    
   
   
       27 . The method of  claim 23 , wherein forming second control gate regions further comprises: 
 forming the second control gate regions along the sidewall regions of the second troughs and separated from the sidewall regions by the second gate dielectric layer, the second gate dielectric layer having an approximate thickness that ranges between 5 nanometers and 10 nanometers.    
   
   
       28 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming a first dielectric layer along sidewall regions of the first troughs;    forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first floating gate regions including a first conductive layer of N+ doped polysilicon;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions including N+ doped polysilicon;    forming first gate lines in the first troughs between opposing first floating gate regions;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    removing material at intersecting portions of first troughs and second troughs to separate the first floating gate regions into first isolated floating gates;    forming a second gate dielectric layer along sidewall regions of the second troughs;    forming second floating gate regions along the sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer, the second floating gate regions including a second conductive layer of N+ doped polysilicon;    forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions including N+ doped polysilicon; and    forming second gate lines in the second troughs between opposing second floating gate regions.    
   
   
       29 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first floating gate regions including a first conductive layer of N+ doped polysilicon;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer, the second floating gate regions including a second conductive layer of N+ doped polysilicon; and    forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.    
   
   
       30 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions including N+ doped polysilicon;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions including N+ doped polysilicon.    
   
   
       31 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    forming first gate lines in the first troughs between opposing first floating gate regions;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer;    forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer; and    forming second gate lines in the second troughs between opposing second floating gate regions.    
   
   
       32 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions are formed together with first gate lines by depositing N+ polysilicon in the first troughs;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions are formed together with second gate lines by depositing N+ polysilicon in the second troughs.    
   
   
       33 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming first floating gate regions along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    removing material at intersecting portions of first troughs and second troughs to separate the first floating gate regions into first isolated floating gates;    forming second floating gate regions along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.    
   
   
       34 . A method, comprising: 
 forming a first source/drain layer at a surface of a substrate;    forming a second source/drain layer at a surface of an epitaxial layer;    etching, in a first direction, a plurality of substantially parallel first troughs in the epitaxial layer;    forming a first gate dielectric layer along sidewall regions of the first troughs;    forming first floating gate regions along the sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    etching, in a second direction substantially orthogonal to the first direction, a plurality of substantially parallel second troughs in the epitaxial layer;    forming a second gate dielectric layer along sidewall regions of the second troughs;    forming second floating gate regions along the sidewall regions of the second troughs and separated from the sidewall regions by the second gate dielectric layer; and    forming second control gate regions between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.