NAND memory arrays

Abstract

A NAND memory array has a first dielectric layer formed on a first portion of a semiconductor substrate and a second dielectric layer formed on a second portion of the semiconductor substrate and adjoining the first dielectric layer. The first dielectric layer is thicker than the second dielectric layer. A first gate stack is formed on the first dielectric layer to form a drain select gate. A string of second gate stacks is formed on the second dielectric layer to form a NAND string of floating-gate memory cells. A first end of the NAND string is coupled in series with the drain select gate. A third gate stack is formed on the second dielectric layer to form a source select gate. A second end of the NAND string is coupled in series with the source select gate.

1 . A NAND memory array, comprising: 
 at least one NAND string of floating gate memory cells comprising: 
 a first dielectric layer formed on a first portion of a semiconductor substrate;  
 a second dielectric layer formed on a second portion of the semiconductor substrate and adjoining the first dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer;  
 a first gate stack formed on the first dielectric layer to form a drain select gate;  
 a string of second gate stacks formed on the second dielectric layer to form the at least one NAND string of floating-gate memory cells, a first end of the at least one NAND string coupled in series with the drain select gate; and  
 a third gate stack formed on the second dielectric layer to form a source select gate, a second end of the at least one NAND string coupled in series with the source select gate.  
   
   
   
       2 . The NAND memory array of  claim 1 , wherein the source and drain select gates and the at least one NAND string form a column of the memory array.  
   
   
       3 . The NAND memory array of  claim 1 , wherein the drain select gate and a first memory cell at the first end of the at least one NAND string share a first source/drain region formed in the substrate and the source select gate and a second memory cell at the second end of the at least one NAND string share a second source/drain region formed in the substrate.  
   
   
       4 . The NAND memory array of  claim 1 , wherein the drain select gate further comprises a drain select line formed on the first dielectric layer, the source select gate further comprises a source select line formed on the second dielectric layer, and each of the memory cells further comprises a floating gate formed on the second dielectric layer, an intergate dielectric layer formed on the floating gate, and a word line formed on the intergate dielectric layer.  
   
   
       5 . The NAND memory array of  claim 1 , wherein each of the memory cells and the select gate further comprise a first conductive layer formed on the second dielectric layer, a third dielectric layer formed on the first conductive layer, and a second conductive layer formed on the third dielectric layer, and wherein the drain select gate comprises the first conductive layer formed on the first dielectric layer, the third dielectric layer formed on the first conductive layer, and the second conductive layer formed on the third dielectric layer.  
   
   
       6 . The NAND memory array of  claim 5 , wherein the first conductive layer is a polysilicon layer.  
   
   
       7 . The NAND memory array of  claim 6 , wherein the polysilicon layer is conductively doped.  
   
   
       8 . The NAND memory array of  claim 5 , wherein the second conductive layer is selected from the group consisting of a polysilicon layer, a metal layer, a metal-containing layer, a layer containing one or more conductive materials, and one or more conductive layers.  
   
   
       9 . The NAND memory array of  claim 5 , wherein the third dielectric layer comprises one or more layers of dielectric material.  
   
   
       10 . The NAND memory array of  claim 1 , wherein each of the first and second dielectric layers are oxide layers.  
   
   
       11 . The NAND memory array of  claim 1 , wherein the second dielectric layer is nitrided.  
   
   
       12 . A NAND memory array comprising: 
 a plurality of rows of memory cells; and    a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;    wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer; and    wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate laterally of the first dielectric layer and adjoining the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer.    
   
   
       13 . The NAND memory array of  claim 12 , wherein the first and second dielectric layers are thermal oxide layers.  
   
   
       14 . The NAND memory array of  claim 12 , wherein the second dielectric layer is a nitride-containing thermal oxide layer.  
   
   
       15 . A memory device, comprising: 
 a memory array, comprising: 
 a plurality of rows of memory cells, the rows respectively connected to corresponding word lines; and  
 a plurality of columns, the respective columns comprising a NAND string of memory cells connected between a source select gate and a drain select gate, each drain select gate selectively coupling the NAND string connected thereto to a bit line;  
 wherein each drain select gate comprises a first gate stack formed on a first dielectric layer formed on a substrate;  
 wherein each of the memory cells of each of the NAND strings comprises a second gate stack formed on a second dielectric layer formed on the substrate laterally of the first dielectric layer and adjoining the first dielectric layer; and  
 wherein each source select gate comprises a third gate stack formed on the second dielectric layer; and  
   column access circuitry connected to the bit lines; and    row access circuitry connected to the word lines.    
   
   
       16 . The memory device of  claim 15 , wherein the first gate stack comprises a drain select line formed on the first dielectric layer, the third gate stack comprises a source select line formed on the second dielectric layer, and the second gate stack comprises a floating gate formed on the second dielectric layer, an intergate dielectric layer formed on the floating gate, and a control gate formed on the intergate dielectric layer and connected to a word line.  
   
   
       17 . The memory device of  claim 15 , wherein the first and second dielectric layers are thermal oxide layers.  
   
   
       18 . The memory device of  claim 15 , wherein the second dielectric layer is a nitride-containing thermal oxide layer.  
   
   
       19 . An electronic system, comprising: 
 a processor; and    at least one memory device coupled to the processor, the at least one memory device comprising: 
 a memory array, comprising: 
 a plurality of rows of memory cells, the rows respectively connected to corresponding word lines; and  
 a plurality of columns, the respective columns comprising a NAND string of memory cells connected between a source select gate and a drain select gate, each drain select gate selectively coupling the NAND string connected thereto to a bit line;  
 wherein each drain select gate comprises a first gate stack formed on a first dielectric layer formed on a substrate;  
 wherein each of the memory cells of each of the NAND strings comprises a second gate stack formed on a second dielectric layer formed on the substrate laterally of the first dielectric layer and adjoining the first dielectric layer; and  
 wherein each source select gate comprises a third gate stack formed on the second dielectric layer; and  
 
 column access circuitry connected to the bit lines; and  
 row access circuitry connected to the word lines.  
   
   
   
       20 . An electronic system, comprising: 
 a processor; and    at least one memory device coupled to the processor, the at least one memory device comprising: 
 a memory array, comprising: 
 a plurality of rows of memory cells; and  
 a plurality of columns of NAND strings of memory cells, each NAND string selectively connected to a bit line through a drain select gate of the respective column;  
 wherein each of the drain select gates comprises a first dielectric layer formed on a semiconductor substrate of the memory array and a control gate formed on the first dielectric layer; and  
 wherein each of the memory cells of each of the NAND strings comprises a second dielectric layer formed on the substrate laterally of the first dielectric layer and adjoining the first dielectric layer, a floating gate formed on the second dielectric layer, a third dielectric layer formed on the floating gate, and a control gate formed on the third dielectric layer, wherein the first dielectric layer is thicker than the second dielectric layer.