Gate controlled floating well vertical MOSFET

Abstract

A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate over-drive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.

1 . A method of fabricating a DRAM cell comprising the steps of: 
 a) forming a deep trench capacitor within a semiconductor substrate, said deep trench being filled with polysilicon and including a first buried strap layer and including a trench top oxide layer above the first buried strap;    b) forming a vertical pass transistor including a gate conductor, a gate oxide and a drain region formed in a p-well by a diffusion in said p-well region outside said deep trench adjacent said first buried strap for conducting voltage to said deep trench capacitor;    c) forming a control cell for controlling the threshold voltage of the vertical pass transistor according to a voltage at a gate connecting a second buried strap and diffusion region formed in the p-well region.    
   
   
       2 . The method according to  claim 1 , wherein a voltage of a gate connecting said second buried strap and diffusion region further controls a gate threshold voltage of the vertical pass transistor, said gate voltage comprising a wordline (WL) voltage controlling access to data stored in said deep trench capacitor via said vertical pass transistor.  
   
   
       3 . The method according to  claim 2 , wherein said gate formed at said storage cell and control cell share a same wordline, the threshold voltage of the storage cell being modified according to the voltage at said wordline.  
   
   
       4 . The method according to  claim 1 , wherein the step c) of forming a control cell including a second buried strap and diffusion region formed in the p-well region, comprises forming said second buried strap region and diffusion region formed in said p-well region of said control cell at a lower depth than the first buried strap region and diffusion region formed in said p-well region of said storage cell, whereby said threshold voltage of the vertical pass transistor is controlled in accordance with a depletion region formed by application of said WL voltage at said second buried strap region and diffusion region in the p-well region.  
   
   
       5 . The method according to  claim 4 , wherein said depletion region formed at said second buried strap and diffusion region extends sufficiently into the p-well to effectively pinch off the p-well to disconnect the p-well region into two regions, a first conductive and second floating p-well region, wherein the floating p-well region enables a lower threshold voltage for turning on said vertical pass transistor during WL active state.  
   
   
       6 . The method according to  claim 4 , wherein said depletion region formed at said second buried strap and diffusion region does not extend sufficiently into the p-well and thus does not effectively pinch off the p-well to disconnect the p-well pinch off the p-well at WL inactive state.  
   
   
       7 . A vertical transistor device comprising: 
 two trenches, each trench including a gate element for the device, a first buried strap forming a corresponding drain or source diffusion region for the device and each located at equal depths within said trenches, and, a second buried strap forming corresponding control diffusions formed in a p-well region separating said two trenches, each second buried strap located at equal depths within said trenches below corresponding first buried straps and electrically connected to said gate for receiving applied voltage thereat,    whereby a voltage threshold of the vertical transistor device is controlled in accordance with depletion regions formed in the p-well at corresponding control diffusions at each said second buried strap in response to application of a gate voltage at each trench.    
   
   
       8 . The vertical transistor device as claimed in  claim 7 , wherein the formed depletion regions extend sufficiently into the p-well to effectively merge and pinch off the p-well region to disconnect the p-well region into two regions, a first conductive and second floating p-well region, wherein the floating p-well region enables a lower voltage threshold for turning on the vertical transistor device.