ZrAlxOy DIELECTRIC LAYERS

Abstract

A ZrAl x O y dielectric layer structured as one or more monolayers and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO 2 . Various embodiments include a ZrAl x O y dielectric film in a variety of electronic arrangements including, but not limited to, capacitors, transistors, memories, and electronic systems.

1 . An electronic device comprising: 
 a substrate; and    a dielectric layer disposed above the substrate, the dielectric layer having a layer of ZrAl x O y , the layer of ZrAl x O y  arranged as a layered structure of one or more monolayers.    
   
   
       2 . The device of  claim 1 , wherein the layer of ZrAl x O y  is substantially a Zr 4 AlO 9  layer.  
   
   
       3 . The device of  claim 2 , wherein an interfacial layer of silicon oxide or a silicate formed between the substrate and the Zr 4 AlO 9  is less than about 1 nm.  
   
   
       4 . The device of  claim 1 , wherein an interfacial layer between the substrate and the layer of ZrAl x O y  is less than about 1 nm.  
   
   
       5 . The device of  claim 1 , wherein the substrate is a silicon-based substrate.  
   
   
       6 . A capacitor, comprising: 
 a first conductive layer disposed above a substrate;    a dielectric layer containing a ZrAl x O y  film disposed on the first conductive layer, the ZrAl x O y  film arranged as a layered structure of one or more monolayers; and    a second conductive layer disposed on the dielectric layer.    
   
   
       7 . The capacitor of  claim 6 , wherein the dielectric layer includes Zr 4 AlO 9 .  
   
   
       8 . The capacitor of  claim 6 , wherein the dielectric layer has an equivalent oxide thickness of 9 Å or less.  
   
   
       9 . The capacitor of  claim 6 , wherein an interfacial layer between the first conductive layer and the ZrAl x O y  is less than about 1 nm.  
   
   
       10 . A transistor comprising: 
 a body region in a substrate between a source region and a drain region;    a dielectric layer disposed above the body region between the source region and the drain region, the dielectric layer having a ZrAl x O y  film, the ZrAl x O y  film arranged as a layered structure of one or more monolayers; and    a gate coupled to the dielectric layer.    
   
   
       11 . The transistor of  claim 10 , wherein the dielectric layer is substantially the ZrAl x O y  film.  
   
   
       12 . The transistor of  claim 10 , wherein the dielectric layer is a floating gate dielectric interposed between a floating gate and a control gate of the transistor.  
   
   
       13 . The transistor of  claim 10 , wherein the dielectric layer is a gate dielectric interposed between a floating gate and the body region.  
   
   
       14 . The transistor of  claim 10 , wherein an interfacial layer between the substrate and the ZrAl x O y  is less than about 1 nm.  
   
   
       15 . The transistor of  claim 10 , wherein the dielectric layer has an equivalent oxide thickness (t eq ) of less than about 10 Angstroms.  
   
   
       16 . A memory comprising: 
 a substrate; and    an array of memory cells, a memory cell of the array having a dielectric layer containing a ZrAl x O y  layer, the dielectric layer disposed above the substrate, the ZrAl x O y  layer arranged as a layered structure of one or more monolayers.    
   
   
       17 . The memory of  claim 16 , wherein the dielectric layer includes Zr 4 AlO 9 .  
   
   
       18 . The memory of  claim 16 , wherein the dielectric layer is a capacitor dielectric of a capacitor in the memory cell.  
   
   
       19 . The memory of  claim 16 , wherein the dielectric layer is a floating gate dielectric interposed between a floating gate and a control gate of a transistor in the memory cell.  
   
   
       20 . The memory of  claim 16 , wherein the dielectric layer is a gate dielectric interposed between a floating gate and a channel of a transistor in the memory cell.  
   
   
       21 . The memory of  claim 16 , wherein an interfacial layer between the substrate and the ZrAl x O y  is less than about 1 nm.  
   
   
       22 . The memory of  claim 16 , wherein the dielectric layer has an equivalent oxide thickness (t eq ) of less than about 10 Angstroms.  
   
   
       23 . The memory of  claim 16 , wherein the substrate is a silicon based substrate.  
   
   
       24 . An electronic system comprising: 
 a processor;    a system bus; and    a memory coupled to the processor by the system bus, the memory including an array of memory cells, a memory cell including a dielectric layer containing a ZrAl x O y  film, the ZrAl x O y  film arranged as a layered structure of one or more monolayers, the dielectric layer disposed above a substrate.    
   
   
       25 . The electronic system of  claim 24 , wherein the dielectric layer includes Zr 4 AlO 9 .  
   
   
       26 . The electronic system of  claim 24 , wherein the dielectric layer is a capacitor dielectric of a storage capacitor in the memory cell.  
   
   
       27 . The electronic system of  claim 24 , wherein the dielectric layer is disposed above a channel of a transistor in the memory cell.  
   
   
       28 . The electronic system of  claim 24 , wherein an interfacial layer between the substrate and the ZrAl x O y  is less than about 1 nm.  
   
   
       29 . The electronic system of  claim 24 , wherein the electronic system includes an information handling device.  
   
   
       30 . The electronic system of  claim 24 , wherein the information handling device includes a wireless device.