Electrical interconnection, and image sensor having the electrical interconnection

Abstract

An electrical interconnection for a highly integrated semiconductor device includes a first insulation layer having at least a first recessed portion on a substrate. The first recessed portion is filled with metal to form a first metal pattern. A diffusion barrier layer including aluminum oxide of high light transmittance is provided on the first insulation layer and the first metal pattern for preventing metal from diffusing. An insulating interlayer including a second recessed portion for exposing an upper surface of the first metal pattern is provided on the diffusion barrier layer. The second recessed portion is filled with metal to form a second metal pattern. The electrical interconnection may be used with an image sensor. The metal may be copper. High light transmittance of the diffusion barrier layer ensures external light reaches the photodetector. The aluminum oxide of the diffusion barrier layer reduces parasitic capacitance of the electrical interconnections.

1 . An electrical interconnection, comprising: 
 a first insulation layer formed on a substrate, the first insulation layer having at least one first recessed portion;    a first metal pattern filling the first recessed portion;    a first diffusion barrier layer formed on the first insulation layer and the first metal pattern, the first diffusion barrier layer preventing metal of the first metal pattern from diffusing out of the first metal pattern, the first diffusion barrier layer including a metal oxide;    a second insulation layer formed on the first diffusion barrier layer, the second insulation layer having at least one second recessed portion that exposes an upper surface of the first metal pattern; and    a second metal pattern filling the second recessed portion.    
   
   
       2 . The electrical interconnection as claimed in  claim 1 , wherein the first diffusion barrier layer has a thickness of about 100 Å to about 500 Å.  
   
   
       3 . The electrical interconnection as claimed in  claim 1 , further comprising an anti-oxidation layer disposed under the diffusion barrier layer, the anti-oxidation layer preventing the first metal pattern from being oxidized.  
   
   
       4 . The electrical interconnection as claimed in  claim 2 , wherein the anti-oxidation layer comprises silicon nitride.  
   
   
       5 . The electrical interconnection as claimed in  claim 3 , wherein the anti-oxidation layer has a thickness less than about 50 Å.  
   
   
       6 . The electrical interconnection as claimed in  claim 1 , wherein the first metal pattern includes copper.  
   
   
       7 . The electrical interconnection as claimed in  claim 1 , wherein the second metal pattern includes copper, and comprises a via contact at a lower portion thereof and a trench contact at an upper portion thereof, the trench contact being electrically connected to the via contact.  
   
   
       8 . The electrical interconnection as claimed in  claim 7 , wherein the second insulation layer includes an insulating interlayer having a lower layer including at least a via-hole exposing a portion of the first metal pattern and an upper layer including at least a trench connected to the via-hole, the via contact and the trench contact being formed along the via-hole and the trench, respectively.  
   
   
       9 . The electrical interconnection as claimed in  claim 8 , further comprising a barrier metal layer on side and bottom surfaces of the via-hole and the trench, the barrier metal layer for preventing the copper from diffusing out of the second metal pattern.  
   
   
       10 . The electrical interconnection as claimed in  claim 8 , further comprising an etching stop layer interposed between the lower layer and the upper layer, the etching stop layer being used for stopping an etching process for forming the trench.  
   
   
       11 . The electrical interconnection as claimed in  claim 8 , wherein the etching stop layer has a thickness of about 300 Å to about 1000 Å.  
   
   
       12 . The electrical interconnection as claimed in  claim 8 , wherein a plurality of the insulating interlayers is stacked on the second insulation layer, each of the plurality of the insulating layers having a second metal pattern including a via contact formed along a via-hole of a corresponding insulating interlayer and a trench contact formed along a trench of a corresponding insulating interlayer, the via contact and the trench contact disposed in adjacent insulating interlayers being electrically connected to each other.  
   
   
       13 . The electrical interconnection as claimed in  claim 12 , further comprising a second diffusion barrier layer interposed between the insulating interlayers, the second diffusion barrier layer preventing a metal material of the trench contact from diffusing into the insulating interlayers.  
   
   
       14 . The electrical interconnection as claimed in  claim 13 , further comprising a metal anti-oxidation layer under the second diffusion barrier layer, the metal anti-oxidation layer preventing the trench contact from being oxidized.  
   
   
       15 . An image device, comprising: 
 a substrate on which a semiconductor device including a optoelectronic device is disposed;    an insulating interlayer structure disposed on the substrate, the insulating interlayer structure including a plurality of insulating interlayer patterns stacked thereon, each of the insulating interlayer patterns including at least a recessed portion;    a plurality of metal patterns positioned along the recessed portions and electrically connected to each other;    a plurality of diffusion barrier layers including a metal oxide and disposed on boundary surfaces between the insulating interlayer patterns and between a metal pattern and an adjacent insulating interlayer, the diffusion barrier layer preventing metal of the metal pattern from diffusing into the insulating interlayers;    a color filter disposed on the insulating interlayer structure; and    a lens disposed on the color filter.    
   
   
       16 . The image device as claimed in  claim 15 , further comprising an anti-oxidation layer under the diffusion barrier layer, the anti-oxidation layer preventing the metal pattern from being oxidized.  
   
   
       17 . The image device as claimed in  claim 15 , wherein each of the metal patterns includes copper, and further comprises a via contact disposed at a lower portion thereof and a conductive line disposed at an upper portion thereof.  
   
   
       18 . The image device as claimed in  claim 15 , between the semiconductor device and the insulating interlayer structure, further comprising: 
 a lower insulation layer covering the semiconductor device; and    a lower contact formed on a portion of the lower insulation layer, the lower contact making electrical contact with the semiconductor device.    
   
   
       19 . The image device as claimed in  claim 18 , further comprising: 
 a lower insulating interlayer formed on the lower insulation layer;    a lower trench contact formed on a portion of the lower insulating interlayer, the lower trench contact being electrically connected with the lower contact; and    a lower diffusion barrier layer including aluminum oxide, the lower diffusion barrier layer being interposed between the lower trench contact and the lower insulating interlayer.    
   
   
       20 . The image device as claimed in  claim 19 , wherein each of the insulating interlayer patterns includes a lower layer pattern formed on the lower diffusion barrier layer and having at least a via-hole for exposing the lower contact and an upper layer pattern having at least a trench electrically connected to the via-hole, each of the metal patterns including copper and further including a via contact formed along the via-hole and a trench contact formed along the trench.  
   
   
       21 . The image device as claimed in  claim 20 , further comprising an etching stop layer interposed between the lower layer pattern and the upper layer pattern, the etching stop layer being used for stopping an etching process for forming the trench.  
   
   
       22 . The image device as claimed in  claim 21 , wherein the etching stop layer comprises aluminum oxide.  
   
   
       23 - 43 . (canceled)  
   
   
       44 . The electrical interconnection as claimed in  claim 1 , wherein the metal oxide is aluminum oxide.  
   
   
       45 . The image device as claimed in  claim 15 , wherein the metal oxide is aluminum oxide.