Ultra-violet protected tamper resistant embedded EEPROM

Abstract

A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.

1 . A semiconductor device comprising: 
 a semiconductor substrate;    a single patterned conductive gate layer that provides all gates of the semiconductor device, including one or more floating gates located over the semiconductor substrate;    a first dielectric layer located over the patterned conductive gate layer;    an amorphous silicon layer located over the first dielectric layer; and    a second dielectric layer located over the amorphous silicon layer.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the patterned conductive gate layer further comprises one or more control gates, each located adjacent to a corresponding one of the floating gates.  
     
     
         3 . The semiconductor device of  claim 2 , wherein each control gate and the adjacent corresponding floating gate comprise inter-digitated regions.  
     
     
         4 . The semiconductor device of  claim 2 , wherein each control gate and the adjacent corresponding floating gate form a portion of an electrically erasable and programmable read only memory (EEPROM) cell.  
     
     
         5 . The semiconductor device of  claim 1 , wherein the patterned conductive gate layer comprises polycrystalline silicon.  
     
     
         6 . The semiconductor device of  claim 1 , further comprising one or more electrically conductive contacts that extend through the first dielectric layer, the amorphous silicon layer and the second dielectric layer, and contact the substrate.  
     
     
         7 . The semiconductor device of  claim 6 , wherein the electrically conductive contacts are in contact with the amorphous silicon layer.  
     
     
         8 . The semiconductor device of  claim 6 , further comprising a first dielectric region located between each of the electrically conductive contacts and the amorphous silicon layer.  
     
     
         9 . The semiconductor device of  claim 8 , further comprising a second dielectric region located between each of the electrically conductive contacts and the amorphous silicon layer, wherein the first and second dielectric regions have different compositions.  
     
     
         10 . The semiconductor device of  claim 6 , further comprising a patterned first metal layer located over the second dielectric layer and in contact with the electrically conductive contacts.  
     
     
         11 . The semiconductor device of  claim 1 , wherein the amorphous silicon layer is in contact with the first and second dielectric layers.  
     
     
         12 . The semiconductor device of  claim 1 , further comprising a first diffusion barrier layer located between the first dielectric layer and the amorphous silicon layer layer.  
     
     
         13 . The semiconductor device of  claim 12 , further comprising a second diffusion barrier layer located between the second dielectric layer and the amorphous silicon layer.  
     
     
         14 . The semiconductor device of  claim 1 , further comprising one or more electrically conductive vias that extend through the first dielectric layer, the amorphous silicon layer and the second dielectric layer, and contact a first metal layer located over the substrate and a second metal layer located over the first metal layer.  
     
     
         15 . The semiconductor device of  claim 14 , wherein the electrically conductive vias are in contact with the amorphous silicon layer.  
     
     
         16 . The semiconductor device of  claim 14 , further comprising a first dielectric region located between each of the electrically conductive vias and the amorphous silicon layer.  
     
     
         17 . The semiconductor device of  claim 16 , further comprising a second dielectric region located between each of the electrically conductive vias and the amorphous silicon layer, wherein the first and second dielectric regions have different compositions.  
     
     
         18 . The semiconductor device of  claim 14 , wherein the amorphous silicon layer is in contact with the first and second dielectric layers.  
     
     
         19 . The semiconductor device of  claim 14 , further comprising a first diffusion barrier layer located between the first dielectric layer and the amorphous silicon layer.  
     
     
         20 . The semiconductor device of  claim 19 , further comprising a second diffusion barrier layer located between the second dielectric layer and the amorphous silicon layer.  
     
     
         21 . A method of fabricating a semiconductor device, comprising: 
 forming a single conductive gate layer over a surface of a semiconductor region;    patterning the single conductive gate layer to create a plurality of gate structures, including one or more floating gates;    forming a first dielectric layer over the gate structures and the semiconductor region;    forming an amorphous silicon layer over the first dielectric layer; and    forming a second dielectric layer over the amorphous silicon layer.    
     
     
         22 . The method of  claim 21 , further comprising patterning the single conductive gate layer to create a control gate adjacent to each of the one or more floating gates.  
     
     
         23 . The method of  claim 21 , wherein each control gate and adjacent floating gate form a portion of an electrically erasable and programmable read only memory (EEPROM) cell.  
     
     
         24 . The method of  claim 21 , wherein the step of forming the single conductive gate layer comprises depositing a layer of polycrystalline silicon.  
     
     
         25 . The method of  claim 21 , further comprising: 
 forming a plurality of contact openings through the first dielectric layer, the amorphous silicon layer and the second dielectric layer; and    forming electrically conductive contacts in the contact openings.    
     
     
         26 . The method of  claim 25 , wherein the step of forming the electrically conductive contacts comprises forming the electrically conductive contacts in contact with the amorphous silicon layer.  
     
     
         27 . The method of  claim 25 , further comprising forming a first dielectric region at locations where the amorphous silicon layer is exposed by the contact openings.  
     
     
         28 . The method of  claim 27 , further comprising forming the first dielectric region by in-situ steam generation (ISSG).  
     
     
         29 . The method of  claim 27 , further comprising forming the first dielectric region by chemical vapor deposition (CVD).  
     
     
         30 . The method of  claim 29 , wherein the first dielectric region comprises tetra-ethoxy-silane (TEOS).  
     
     
         31 . The method of  claim 27 , further comprising forming a second dielectric region over the first dielectric region, wherein the first and second dielectric regions have different compositions.  
     
     
         32 . The method of  claim 25 , further comprising forming a patterned first metal layer over the second dielectric layer and in contact with the electrically conductive contacts.  
     
     
         33 . The method of  claim 32 , wherein the step of forming the electrically conductive contacts comprises contacting the semiconductor region.  
     
     
         34 . The method of  claim 32 , further comprising forming a patterned second metal layer over the patterned first metal layer, wherein the electrically conductive contacts contact the patterned first and second metal layers.  
     
     
         35 . The method of  claim 21 , further comprising forming the first dielectric layer, the amorphous silicon layer and the second dielectric layer such that the amorphous silicon layer is in contact with the first dielectric layer and the second dielectric layer.  
     
     
         36 . The method of  claim 21 , further comprising forming a first diffusion barrier layer between the first dielectric layer and the amorphous silicon layer.  
     
     
         37 . The method of  claim 36 , further comprising forming a second diffusion barrier layer between the second dielectric layer and the amorphous silicon layer.