Ultra high density flash memory

Abstract

An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for four vertical floating gate transistors that have individual floating and control gates distributed on the four sides of the pillar. Mutually orthogonal first gate lines and second gate lines provide addressing of the control gates. First source/drain terminals are row addressable by interconnection lines disposed substantially parallel to the first gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the second gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F 2 is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F 2 is needed per bit of data.

1 . A memory array formed on a substrate, comprising: 
 a first source/drain layer positioned on a surface of the substrate;    a semiconductor epitaxial layer positioned on the first source/drain layer;    a second source/drain layer positioned on a surface of the epitaxial layer;    a plurality of parallel first troughs positioned in the epitaxial layer that extend in a first direction;    a first gate dielectric layer adjacent to sidewall regions of the first troughs;    a first conductive layer in the first troughs;    floating gate regions that are positioned along the sidewall regions and separated from the sidewall regions by the first gate dielectric layer;    a first intergate dielectric layer positioned on exposed portions of the floating gate regions in the first troughs;    first gate lines positioned in the underlying etched portion of the substrate between opposing floating gate regions in the first troughs; and    control gate regions positioned in the first troughs and positioned between opposing floating gate regions and separated therefrom by the first intergate dielectric layer.    
   
   
       2 . The memory array of  claim 1 , further comprising: 
 a plurality of parallel second troughs positioned in the epitaxial layer that extend in a second direction that is substantially orthogonal to the first direction;    a second gate dielectric layer adjacent to sidewall regions of the second troughs;    a second conductive layer in the second troughs;    floating gate regions that are positioned along the sidewall regions and separated from the sidewall regions by the second gate dielectric layer;    a second intergate dielectric layer positioned on exposed portions of the floating gate regions in the second troughs; and    control gate regions and second gate lines positioned between opposing floating gate regions in the second troughs by the second intergate dielectric layer.    
   
   
       3 . The memory array of  claim 1 , wherein the substrate further comprises: 
 a bulk semiconductor.    
   
   
       4 . The memory array of  claim 1 , wherein the substrate further comprises: 
 a semiconductor on insulator portion.    
   
   
       5 . The memory array of  claim 1 , further comprising an insulating layer formed by undercutting semiconductor regions between the first troughs.  
   
   
       6 . The memory array of  claim 2 , further comprising: 
 a thin silicon nitride oxidation barrier layer formed by chemical vapor deposition on the sidewall regions of the second troughs;    bottom portions of the second troughs formed by removing the thin silicon nitride oxidation barrier layer to expose the bottom portions; and    a bottom insulation layer formed on the bottom portions of the second troughs by thermal oxidation.    
   
   
       7 . A memory array, comprising: 
 a first source/drain layer formed at a surface of a substrate;    a second source/drain layer formed at a surface of an epitaxial layer, the epitaxial layer being positioned on the first source/drain layer and comprising P-silicon;    a thin layer of silicon dioxide formed on the second source/drain layer;    a layer of silicon nitride formed on the thin layer of silicon dioxide;    a plurality of parallel troughs that extend into the epitaxial layer;    at least two floating gate regions formed along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    gate lines positioned between opposing floating gate regions in the troughs; and    control gate regions positioned in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       8 . The memory array of  claim 7 , wherein the first source/drain layer further comprises a first source/drain layer having a thickness ranging between approximately 0.2 microns and approximately 0.5 microns.  
   
   
       9 . The memory array of  claim 7 , wherein the thin layer of silicon dioxide further comprises a thin layer of silicon dioxide having a thickness of approximately 10 nanometers.  
   
   
       10 . A memory array, comprising: 
 a first source/drain layer positioned on a surface of a substrate, the first source/drain comprising N+ silicon formed by epitaxial growth of silicon upon the substrate;    a semiconductor epitaxial layer positioned on the first source/drain layer;    a second source/drain layer positioned on a surface of the semiconductor epitaxial layer, the second source/drain layer comprising N+ silicon and having an approximate thickness of 150 nanometers;    a thin layer of silicon dioxide positioned on the second source/drain layer, the thin layer of silicon dioxide having an approximate thickness of 10 nanometers;    a layer of silicon nitride positioned on the thin layer of silicon dioxide, the layer of silicon nitride having an approximate thickness of 200 nanometers;    a plurality of parallel troughs that extend into the epitaxial layer;    at least two floating gate regions positioned along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    gate lines positioned between opposing floating gate regions in the troughs; and    control gate regions positioned in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       11 . The memory array of  claim 10 , wherein the first source/drain layer further comprises a first source/drain layer having a thickness ranging between approximately 0.2 microns and approximately 0.5 microns.  
   
   
       12 . The memory array of  claim 10 , wherein the at least two floating gate regions further comprise at least two floating gate regions positioned along the sidewall regions of the troughs and separated from the sidewall regions by the gate dielectric layer, the gate dielectric layer having an a thickness that ranges between approximately 5 nanometers and approximately 10 nanometers.  
   
   
       13 . A memory array, comprising: 
 a first source/drain layer formed at a surface of a substrate, the substrate comprised of a semiconductor-on-insulator portion, and the a first source/drain layer comprising N+ silicon formed by ion implantation of donor dopants into the substrate;    a semiconductor epitaxial layer formed on the first source/drain layer, the semiconductor epitaxial layer comprising P− silicon and having an approximate thickness of 0.6 microns;    a second source/drain layer formed at a surface of the epitaxial layer, the second source/drain layer comprising N+ silicon and having an approximate thickness of 150 nanometers;    a thin layer of silicon dioxide formed on the second source/drain layer;    a layer of silicon nitride formed on the thin layer of silicon dioxide;    a plurality of parallel troughs extending into the epitaxial layer;    at least two floating gate regions formed along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    gate lines formed between opposing floating gate regions in the troughs; and    control gate regions formed in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       14 . The memory array of  claim 13 , further comprising: 
 a conductive layer formed in the troughs.    
   
   
       15 . A memory array, comprising: 
 a first source/drain layer positioned on a surface of a substrate, the first source/drain comprising N+ silicon formed by ion implantation of donor dopants into the substrate;    a second source/drain layer positioned on a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer and comprising P-silicon;    a thin layer of silicon dioxide on the second source/drain layer;    a layer of silicon nitride on the thin layer of silicon dioxide;    a plurality of parallel troughs extending into the epitaxial layer;    an insulating layer undercutting semiconductor regions between the troughs;    at least two floating gate regions positioned along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer;    gate lines positioned between opposing floating gate regions in the troughs; and    control gate regions positioned in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer.    
   
   
       16 . The memory array of  claim 15 , wherein the at least two floating gate regions further comprise at least two floating gate regions formed along the sidewall regions of the troughs and separated from the sidewall regions by the gate dielectric layer, the gate dielectric layer having a thickness that ranges between approximately 5 nanometers and approximately 10 nanometers.  
   
   
       17 . The memory array of  claim 15 , wherein the control gate regions further comprise control gate regions formed in the troughs between opposing floating gate regions and separated therefrom by an intergate dielectric layer, the intergate dielectric layer having a thickness that ranges between approximately 7 nanometers and approximately 15 nanometers.  
   
   
       18 . A memory array, comprising: 
 a first source/drain layer formed at a surface of a substrate;    a second source/drain layer formed at a surface of an epitaxial layer, the epitaxial layer being formed on the first source/drain layer;    a plurality of parallel troughs formed in the epitaxial layer;    a thin silicon nitride oxidation barrier layer formed using by chemical vapor deposition on sidewall regions of the troughs;    bottom portions of the troughs exposed by anisotropically etching the thin silicon nitride oxidation barrier layer;    a bottom insulation layer on the bottom portions of the troughs that is formed by thermal oxidation;    at least two floating gate regions formed along sidewall regions of the troughs and separated from the sidewall regions by a gate dielectric layer; and    control gate regions formed in the troughs and between opposing floating gate regions that are separated therefrom by an intergate dielectric layer.    
   
   
       19 . The memory array of  claim 18 , wherein the first source/drain layer further comprises: 
 a first source/drain layer formed at the surface of the substrate, wherein the substrate is a bulk semiconductor.    
   
   
       20 . A memory array, comprising: 
 a first source/drain layer positioned on a surface of a substrate;    a second source/drain layer positioned on a surface of an epitaxial layer;    a plurality of parallel first troughs positioned in the epitaxial layer and extending in a first direction;    a first bottom insulation layer positioned on bottom portions of the first troughs;    first floating gate regions positioned along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    first control gate regions positioned between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    a plurality of parallel second troughs positioned in the epitaxial layer and extending in a second direction substantially orthogonal to the first direction;    second floating gate regions positioned along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    second control gate regions positioned in the second troughs between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.    
   
   
       21 . The memory array of  claim 20 , further comprising: 
 a second bottom insulation layer positioned on bottom portions of the second troughs.    
   
   
       22 . The memory array of  claim 20 , wherein the first floating gate regions further comprise: 
 first floating gate regions positioned along the sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first gate dielectric layer having a thickness that ranges between approximately 5 nanometers and approximately 10 nanometers.    
   
   
       23 . The memory array of  claim 20 , wherein the second control gate regions further comprise: 
 second control gate regions positioned along the sidewall regions of the second troughs and separated from the sidewall regions by the second gate dielectric layer, the second gate dielectric layer having a thickness that ranges between approximately 5 nanometers and approximately 10 nanometers.    
   
   
       24 . A memory array, comprising: 
 a first source/drain layer formed at a surface of a substrate;    a second source/drain layer formed at a surface of an epitaxial layer;    a plurality of parallel first troughs formed in the epitaxial layer and extending in a first direction;    a first dielectric layer formed along sidewall regions of the first troughs;    first floating gate regions formed along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first floating gate regions including a first conductive layer of N+ doped polysilicon;    first control gate regions formed between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, wherein the first control gate regions comprise N+ doped polysilicon;    first gate lines formed in the first troughs and between opposing first floating gate regions;    a plurality of parallel second troughs formed in the epitaxial layer and extending in a second direction substantially orthogonal to the first direction, wherein the first troughs and the second troughs intersect by removing material to separate the first floating gate regions into first isolated floating gates;    a second gate dielectric layer formed along sidewall regions of the second troughs;    second floating gate regions formed along the sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer, the second floating gate regions including a second conductive layer of N+ doped polysilicon;    second control gate regions formed between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions including N+ doped polysilicon; and    second gate lines in the second troughs between opposing second floating gate regions.    
   
   
       25 . A memory array, comprising: 
 a first source/drain layer positioned at a surface of a substrate;    a second source/drain layer positioned at a surface of an epitaxial layer;    a plurality of parallel first troughs positioned in the epitaxial layer that extend in a first direction;    first floating gate regions positioned along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer, the first floating gate regions including a first conductive layer of N+ doped polysilicon;    first control gate regions positioned between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    a plurality of parallel second troughs formed in the epitaxial layer that extend in a second direction substantially orthogonal to the first direction;    second floating gate regions formed along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer, the second floating gate regions including a second conductive layer of N+ doped polysilicon; and    second control gate regions positioned between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.    
   
   
       26 . A memory array, comprising: 
 a first source/drain layer located on a surface of a substrate;    a second source/drain layer located on a surface of an epitaxial layer;    a plurality of parallel first troughs formed in the epitaxial layer and extending in a first direction;    first floating gate regions formed along sidewall regions of the first troughs and separated from the sidewall regions by the first gate dielectric layer;    first control gate regions formed between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions including N+ doped polysilicon;    a plurality of parallel second troughs formed by etching the epitaxial layer, the second troughs extending in a second direction substantially orthogonal to the first direction;    second floating gate regions formed along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    second control gate regions formed between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions including N+ doped polysilicon.    
   
   
       27 . A semiconductor memory device, comprising: 
 a first source/drain layer formed at a surface of a substrate;    a second source/drain layer formed at a surface of an epitaxial layer;    a plurality of parallel first troughs formed in the epitaxial layer and extending in a first direction;    first floating gate regions formed along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    first control gate regions formed between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    first gate lines formed in the first troughs between opposing first floating gate regions;    a plurality of parallel second troughs formed in the epitaxial layer that extend in a second direction substantially orthogonal to the first direction;    second floating gate regions formed along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer;    second control gate regions formed between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer; and    second gate lines formed in the second troughs between opposing second floating gate regions.    
   
   
       28 . A semiconductor memory device, comprising: 
 a first source/drain layer formed at a surface of a substrate;    a second source/drain layer formed at a surface of an epitaxial layer;    a plurality of parallel first troughs etched in the epitaxial layer and extending in a first direction;    first floating gate regions formed along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    first control gate regions formed between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer, and the first control gate regions are formed together with first gate lines by depositing N+ polysilicon in the first troughs;    a plurality of parallel second troughs etched in the epitaxial layer and extending in a second direction substantially orthogonal to the first direction;    second floating gate regions formed along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    second control gate regions formed between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer, and the second control gate regions are formed together with second gate lines by depositing N+ polysilicon in the second troughs.    
   
   
       29 . A semiconductor memory device, comprising: 
 a first source/drain layer positioned at a surface of a substrate;    a second source/drain layer positioned at a surface of an epitaxial layer;    a plurality of parallel first troughs etched in the epitaxial layer that extend in a first direction;    first floating gate regions positioned along sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    first control gate regions positioned between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    a plurality of parallel second troughs etched in the epitaxial layer that extend in a second direction substantially orthogonal to the first direction, the material being removed at intersecting portions of the first troughs and the second troughs to separate the first floating gate regions into first isolated floating gates;    second floating gate regions positioned along sidewall regions of the second troughs and separated from the sidewall regions by a second gate dielectric layer; and    second control gate regions positioned between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.    
   
   
       30 . A semiconductor memory device, comprising: 
 a first source/drain layer formed at a surface of a substrate;    a second source/drain layer formed at a surface of an epitaxial layer;    a plurality of parallel first troughs formed in the epitaxial layer and extending in a first direction;    a first gate dielectric layer formed along sidewall regions of the first troughs;    first floating gate regions formed along the sidewall regions of the first troughs and separated from the sidewall regions by a first gate dielectric layer;    forming first control gate regions between opposing first floating gate regions, the first control gate regions being separated from the first floating gate regions by a first intergate dielectric layer;    a plurality of parallel second troughs formed in the epitaxial layer and extending in a second direction substantially orthogonal to the first direction;    a second gate dielectric layer formed along sidewall regions of the second troughs;    second floating gate regions formed along the sidewall regions of the second troughs and separated from the sidewall regions by the second gate dielectric layer; and    second control gate regions formed between opposing second floating gate regions, the second control gate regions being separated from the second floating gate regions by a second intergate dielectric layer.