US2006254716A1PendingUtilityA1

Processing system and method for chemically treating a tera layer

Assignee: TOKYO ELECTRON LTDPriority: Jul 6, 2004Filed: Jul 14, 2006Published: Nov 16, 2006
Est. expiryJul 6, 2024(expired)· nominal 20-yr term from priority
H10P 14/6922H10P 14/6336H10P 76/4085H10P 76/2043H10P 76/405H10P 14/6905
49
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Claims

Abstract

A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.

Claims

exact text as granted — not AI-modified
1 . A system for processing a Tunable Etch Rate ARC (TERA) layer on a substrate, comprising: 
 a processing subsystem for depositing the TERA layer on the substrate using a plasma enhanced chemical vapor deposition (PECVD) system;    a processing subsystem for creating features in the TERA layer using an etching system; and    a processing subsystem for reducing the size of the features in the TERA layer.    
   
   
       2 . The system of  claim 1 , further comprising: 
 a substrate holder in a processing chamber in the PECVD system; and    means for providing a process gas to the processing chamber, wherein the process gas comprises an inert gas and a silicon-containing precursor, or a carbon-containing precursor, or a combination thereof.    
   
   
       3 . The system of  claim 2 , further comprising: 
 an upper electrode coupled to the processing chamber; and    a translation device coupled to the substrate holder for establishing a gap between an upper electrode surface and a surface of the substrate holder.    
   
   
       4 . The system of  claim 3 , wherein the gap ranges from approximately 10 mm to approximately 200 mm.  
   
   
       5 . The system of  claim 2 , further comprising: 
 a first RF source coupled to the upper electrode, wherein the first RF source operates in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. and operates in a power range from approximately 10 watts to approximately 10000 watts.    
   
   
       6 . The system of  claim 5 , further comprising: 
 a second RF source coupled to the substrate holder, wherein the second RF source operates in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. and operates in a power range from approximately 10 watts to approximately 10000 watts.    
   
   
       7 . The system of  claim 2 , further comprising: 
 an RF source coupled to the substrate holder, wherein the RF source operates in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. and operates in a power range from approximately 10 watts to approximately 10000 watts.    
   
   
       8 . The system of  claim 2 , wherein the silicon-containing precursor comprises monosilane (SiH 4 ), tetraethylorthosilicate (TEOS), monomethylsilane (1 MS), dimethylsilane (2MS), trimethylsilane (3MS), tetramethylsilane (4MS), octamethylcyclotetrasiloxane (OMCTS), dimethyldimethoxysilane (DMDMOS), or tetramethylcyclotetrasilane (TMCTS), or a combination of two or more thereof.  
   
   
       9 . The system of  claim 2 , wherein the carbon-containing precursor comprises CH 4 , C 2 H 4 , C 2 H 2 , C 6 H 6 , or C 6 H 5 OH, or a combination of two or more thereof.  
   
   
       10 . The system of  claim 2 , wherein the first process gas includes an inert gas comprising argon, helium, or and nitrogen, or a combination of two or more thereof.

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