Memory devices and access methods

Abstract

Apparatus, systems, and methods may operate to receive an external row address, receive a pipeline/burst select signal, select an external address path if the pipeline/burst signal indicates a pipeline mode of operation, and select an internal address path if the pipeline/burst signal indicates a burst mode of operation.

1 . A method of specifying burst or pipeline access to a memory, comprising: 
 receiving an external row address;    receiving a pipeline/burst select signal;    selecting an external address path if the pipeline/burst signal indicates a pipeline mode of operation; and    selecting an internal address path if the pipeline/burst signal indicates a burst mode of operation.    
   
   
       2 . The method of  claim 1 , wherein selecting the external address path includes selecting the external address path from a buffer.  
   
   
       3 . The method of  claim 1 , further including: 
 generating an internal column address after selecting the internal data path.    
   
   
       4 . The method of  claim 1 , further including: 
 obtaining a second external column address subsequent to receiving a first external column address during the pipeline mode of operation.    
   
   
       5 . The method of  claim 1 , further including: 
 generating an internal column address patterned after an external column address during the burst mode of operation.    
   
   
       6 . A memory device, including: 
 external address inputs to receive an external row address;    a pin to receive a pipeline/burst select signal; and    control logic to select an external address path if the pipeline/burst signal indicates a pipeline mode of operation, and to select an internal address path if the pipeline/burst signal indicates a burst mode of operation.    
   
   
       7 . The memory device of  claim 6 , further including: 
 selection circuitry to couple to the control logic and to select between a read operation and a write operation.    
   
   
       8 . The memory device of  claim 6 , comprising an asynchronous memory device.  
   
   
       9 . The memory device of  claim 6 , furthering including: 
 a temporary storage device to couple to the external address path and the internal address path.    
   
   
       10 . The memory device of  claim 9 , further including: 
 a decoder to receive the external row address from the temporary storage device.    
   
   
       11 . The memory device of  claim 9 , further including: 
 a counter to couple to the temporary storage device, and to receive the external row address to generate an internal address.    
   
   
       12 . The memory device of  claim 6 , further including: 
 asynchronous dynamic random access memory cells to couple to the control logic.    
   
   
       13 . The memory device of  claim 6 , further including: 
 a column address decoder to couple to the control logic and to receive an external column address.    
   
   
       14 . The memory device of  claim 6 , wherein the pipeline mode of operation comprises a pipeline extended data out operation.  
   
   
       15 . The memory device of  claim 6 , wherein the burst mode of operation comprises a burst extended data out operation.  
   
   
       16 . The memory device of  claim 6 , wherein the control logic includes: 
 at least one multiplexed device.    
   
   
       17 . A system comprising: 
 a microprocessor; and    a memory having a pipeline/burst signal input to couple to the microprocessor, the memory operable to select an external address path if the pipeline/burst signal indicates a pipeline mode of operation, and to select an internal address path if the pipeline/burst signal indicates a burst mode of operation.    
   
   
       18 . The system of  claim 17 , further including: 
 a plurality of addressable memory arrays to couple to the microprocessor.    
   
   
       19 . The system of  claim 17 , wherein the memory comprises a dynamic random access memory.  
   
   
       20 . The system of  claim 17 , wherein the memory comprises an asynchronous memory.