Method of forming polysilicon layers in a transistor
Abstract
A semiconductor transistor which is not capable of storing data is formed as follows. An insulating layer is formed over a silicon region. An undoped polysilicon layer is formed over and in contact with the insulating layer. A doped polysilicon layer is formed over and in contact with the undoped polysilicon layer such that at least two edges of the doped polysilicon layer vertically line up with corresponding edges of the undoped polysilicon layer to thereby form sidewalls, and the doped and undoped polysilicon layers form a gate of the transistor. After the doped polysilicon layer is formed, source and drain regions are formed in the silicon region. Dopants from the doped polysilicon layer migrate into the undoped polysilicon layer thereby doping the undoped polysilicon layer.
Claims
exact text as granted — not AI-modified1 . A method of forming a semiconductor transistor, comprising:
forming an insulating layer over a silicon region; forming an undoped polysilicon layer over and in contact with the insulating layer; forming a doped polysilicon layer over and in contact with the undoped polysilicon layer such that at least two edges of the doped polysilicon layer vertically line up with corresponding edges of the undoped polysilicon layer to thereby form sidewalls, the doped and undoped polysilicon layers forming a gate of the transistor; and after the doped polysilicon layer forming act, forming source and drain regions in the silicon region, wherein dopants from the doped polysilicon layer migrate into the undoped polysilicon layer thereby doping the undoped polysilicon layer, and the semiconductor transistor is not capable of storing data.
2 . The method of claim 1 wherein the insulating layer is a gate oxide layer.
3 . The method of claim 1 wherein a thickness of the doped polysilicon layer is greater than a thickness of the undoped polysilicon layer by a factor in the range of two to four.
4 . The method of claim 1 further comprising:
forming insulating spacers along the sidewalls of the doped and undoped polysilicon layers.
5 . The method of claim 1 wherein said doped polysilicon layer forming act comprises depositing an in-situ doped polysilicon layer.
6 . The method of claim 1 wherein the transistor is any one of a NMOS transistor, PMOS transistor, enhancement transistor, and depletion transistor.
7 . The method of claim 1 wherein the doped polysilicon layer has a doping concentration and a thickness greater than a thickness of the undoped polysilicon layer so as to prevent polysilicon depletion in the gate.
8 . The method of claim 1 further comprising:
forming a conductive layer comprising tungsten over and in contact with the doped polysilicon layer.Join the waitlist — get patent alerts
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