Apparatus and method for adjusting clock skew

Abstract

The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the address and data signals which exhibit reduced skew. When a skewed external noninverse clock signal and a corresponding external inverse clock signal are passed through respective reference voltage input buffers there is no reduction in skew between the two internal signals. In a preferred embodiment, the invention provides back to back inverters connected to both lines carrying the noninverted and inverted internal clock signals. The slower internal clock signal has an extra inverter driving it when it switches states and the faster internal clock signal has an extra inverter fighting it when it switches states. The skew of the two signals is reduced, allowing for faster operation of the integrated circuit and a reduction in misread data signals.

1 - 98 . (canceled)  
   
   
       99 . A synchronous memory device comprising: 
 an array of memory cells;    at least one clock input for receiving at least one clock signal and for producing first and second internal clock signals;    a circuit for reducing skew between the first and second internal clock signals; and    first and second input buffer circuits for receiving first and second external signals,    wherein each of said first and second input buffer circuits comprises: 
 an input for receiving an external signal;  
 an input for receiving a reference voltage signal;  
 a differential amplifier coupled to said input, said differential amplifier having an output terminal for providing a latch signal in response to the external signal in comparison to the reference voltage signal, the latch signal having a first or second state;  
 a buffer circuit inverter connected to said output terminal of said differential amplifier, said buffer circuit inverter generating a first internal signal when the latch signal is in a first state, and a second internal signal when the latch signal is in a second state; and  
 an input line for transmitting said first or second internal signal, said input line connected to one of said first and second signal input/output lines.  
   
   
   
       100 . The synchronous memory device of  claim 99 , wherein said circuit for reducing skew comprises: 
 first and second clock signal input/output lines for receiving and transmitting first and second internal clock signals, respectively; and    at least first and second inverters each having an input and an output, said input of said first inverter connected to said output of said second inverter and to said first clock signal input/output line and said input of said second inverter connected to said output of said first inverter and to said second clock signal input/output line.    
   
   
       101 . The synchronous memory device of  claim 100 , wherein said circuit for reducing skew further comprises an enable circuit for receiving an enable signal and enabling or disabling said first and second inverters in response to the enable signal.  
   
   
       102 . The synchronous memory device of  claim 100 , wherein said enable circuit comprises: 
 a first voltage source for supply of a first voltage to said first inverter and said second inverter, said first voltage supply being gated to said inverters by the enable signal;    an enable inverter for inverting the enabling signal; and    a second voltage source for supplying a second voltage to said second inverter and said first inverter, said second voltage source being gated to said first and second inverters by the inverted enable signal.    
   
   
       103 . The synchronous memory device of  claim 101 , wherein said first voltage source is gated by a P-channel transistor responsive to the enable signal.  
   
   
       104 . The synchronous memory device of  claim 101 , wherein said second voltage source is gated by a N-channel transistor responsive to the inverse of the enable signal.  
   
   
       105 . The synchronous memory device of  claim 101 , wherein said first voltage source is gated by an N-channel transistor responsive to the enable signal.  
   
   
       106 . The synchronous memory device of  claim 101 , wherein said second voltage source is gated by an P-channel transistor responsive to the inverse of the enable signal.  
   
   
       107 . The synchronous memory device of  claim 100 , further comprising an enable circuit for receiving said enable signal and enabling or disabling said first and second input buffer circuits in response to the enable signal.  
   
   
       108 . The synchronous memory device of  claim 100 , further comprising a first and second driver circuit for boosting said output signal, said first and second driver circuit connected to said first and second clock signal input/output lines, respectively.  
   
   
       109 . The synchronous memory device of  claim 108 , wherein at least one of said first and second driver circuits comprises at least a first and second driver inverter connected in series.  
   
   
       110 . The synchronous memory device of  claim 109 , further comprising at least a third driver inverter connected in parallel to said first and second driver inverters, the output of said third driver inverter gating the output of said first and second driver inverters to a predetermined voltage.