Asynchronously-accessible memory devices and access methods

Abstract

Apparatus and methods may operate to switch between burst modes and pipelined modes without using a WCBR (write and column address select before row address select) cycle, as well as to select an external address data path, instruct a memory to perform a desired memory operation, and perform the desired memory operation until terminated.

1 . A method of accessing an asynchronous memory, including: 
 switching between a burst extended data out (EDO) mode and a pipelined EDO mode without using a WCBR (write and column address select before row address select) cycle;    selecting an external address data path;    instructing the asynchronous memory to perform a desired memory operation; and    performing the desired memory operation until terminated.    
   
   
       2 . The method of  claim 1 , wherein the selecting includes selecting the external address data path from a buffer when the switching switches to the burst EDO mode.  
   
   
       3 . The method of  claim 1 , wherein the desired memory operation is selected from a group consisting of a read operation and a write operation.  
   
   
       4 . The method of  claim 1 , wherein the performing includes obtaining an external column address to perform the desired memory operation.  
   
   
       5 . The method of  claim 4 , wherein the performing includes iterating the obtaining until terminated.  
   
   
       6 . The method of  claim 1 , wherein the performing includes generating an internal column address to perform the desired memory operation.  
   
   
       7 . The method of  claim 6 , wherein the generating includes iterating the generating until terminated.  
   
   
       8 . The method of  claim 1 , further including: 
 obtaining a first external column address; and    accessing the asynchronous memory when the switching switches to the pipeline EDO mode.    
   
   
       9 . The method of  claim 8 , further including: 
 obtaining a second external column address subsequent to receiving the first external column address during operation in the pipelined EDO mode.    
   
   
       10 . The method of  claim 1 , further including: 
 generating an internal column address subsequent to receiving an external column address during operation in the burst EDO mode, the internal column address patterned after the external column address.    
   
   
       11 . The method of  claim 1 , further including: 
 selecting an internal address pathway based on the switching between the burst EDO mode and the pipelined EDO mode.    
   
   
       12 . The method of  claim 1 , wherein the selecting further including: 
 selecting an initial buffered external address data path;    obtaining an initial external column address;    accessing the asynchronous memory; and    generating internal column addresses when the switching switches to the burst EDO mode.    
   
   
       13 . An asynchronous memory device, including: 
 mode selection circuitry configured to select between a burst extended data out (EDO) mode and a pipelined EDO mode;    an external column address data path to operate during pipelined EDO mode operations;    an internal column address generation module to operate during burst EDO mode operations; and    pipelined/burst circuitry to couple to the mode selection circuitry and to switch between the pipelined EDO mode and the burst EDO mode without using a WCBR (write and column address select before row address select) cycle.    
   
   
       14 . The asynchronous memory device of  claim 13 , further including: 
 selection circuitry for selecting between a read operation and a write operation.    
   
   
       15 . The asynchronous memory device of  claim 13 , wherein the pipelined EDO mode operations include read and write operation column address retrieval.  
   
   
       16 . The asynchronous memory device of  claim 13 , wherein the burst EDO mode operations include read and write operation column address generation.  
   
   
       17 . The asynchronous memory device of  claim 13 , further including: 
 an external mode selection pin coupled to the mode selection circuitry.    
   
   
       18 . The asynchronous memory device of  claim 13 , further including: 
 asynchronous dynamic random access memory cells to couple to the internal column address generation module.    
   
   
       19 . The asynchronous memory device of  claim 13 , wherein the piplined/burst circuitry includes a buffer to store an address.  
   
   
       20 . The asynchronous memory device of  claim 19 , wherein the piplined/burst circuitry includes at least one counter to increment the address.