FABRICATION OF AN EEPROM CELL WITH SiGe SOURCE/DRAIN REGIONS

Abstract

An EEPROM memory cell uses silicon-germanium/silicon and emitter polysilicon film for fabricating shallow source/drain regions to increase a breakdown voltage with respect to a well. The source/drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

1 . An electronic integrated circuit comprising: 
 a first PMOS transistor configured to control an operation of a memory transistor;    a second PMOS transistor configured to operate as a memory transistor with a floating programming gate and coupled to the first PMOS transistor, the second PMOS transistor configured to have a programming voltage from 12 to 15 volts, the first PMOS transistor and the second PMOS transistor configured to operate as an EEPROM cell; and    at least one bipolar device, the at least one bipolar device being in electrical communication with the select transistor and the memory transistor and configured to have a breakdown voltage greater than or equal to the programming voltage of the NMOS transistor.    
   
   
       2 . The electronic integrated circuit of  claim 1 , wherein the first PMOS transistor comprises a source dopant region and a combination drain/source dopant region, wherein all the dopant regions are doped to a depth of about 100 nm.  
   
   
       3 . The electronic, integrated circuit of  claim 1 , wherein the second PMOS transistor comprises a combination drain/source dopant region, a gate dopant region, and a drain dopant region that are all doped to a depth of about 100 nm, the second PMOS transistor further comprises a floating programming gate located in proximity to the gate dopant region.  
   
   
       4 . The electronic integrated circuit of  claim 3 , wherein the gate dopant region is coupled to the drain dopant region.  
   
   
       5 . The electronic integrated circuit of  claim 1 , wherein the second PMOS transistor further comprises a tunnel diode window.  
   
   
       6 . The electronic integrated circuit of  claim 5 , wherein an oxide in the tunnel diode window is about 7 nm thick.  
   
   
       7 . An electronic integrated circuit comprising: 
 a PMOS transistor configured to control an operation of a memory transistor;    an NMOS transistor configured to operate as a memory transistor with a floating programming gate and coupled to the PMOS transistor, the NMOS transistor configured to have a programming voltage of 9 to 11 volts, the PMOS transistor and the NMOS transistor configured to operate as an EEPROM cell; and    at least one bipolar device, the at least one bipolar device being in electrical communication with the select transistor and the memory transistor and configured to have a breakdown voltage greater than or equal to the programming voltage of the NMOS transistor.    
   
   
       8 . The electronic integrated circuit of  claim 7 , wherein the PMOS transistor comprises a PMOS drain dopant region and a PMOS source dopant region, which are all doped to a depth of about 100 nm.  
   
   
       9 . The electronic integrated circuit of  claim 7 , wherein the NMOS transistor comprises an NMOS drain dopant region, an NMOS gate dopant region, and an NMOS source dopant region, wherein all the dopant regions are doped to a depth of about 100 nm, the NMOS transistor further comprises a floating programming gate located in proximity to the gate dopant region.  
   
   
       10 . The electronic integrated circuit of  claim 9 , wherein the gate dopant region is coupled to the second drain dopant region.  
   
   
       11 . The electronic integrated circuit of  claim 7 , wherein the PMOS transistor comprises a first drain dopant region and a first source dopant region, the NMOS transistor comprises a second drain dopant region, a gate dopant region, and a second source dopant region, wherein the first drain dopant region is coupled to the second drain dopant region, the PMOS transistor and the NMOS transistor configured to operate as an EEPROM cell.  
   
   
       12 . The electronic integrated circuit of  claim 7 , wherein the NMOS transistor further comprises a tunnel diode window.  
   
   
       13 . The electronic integrated circuit of  claim 12 , wherein an oxide in the tunnel diode window is about 7 nm thick.