Semiconductor substrate cleaning

Abstract

Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H 2 SO 4 ) solution. The H 2 SO 4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H 2 SO 4 solution with hydrogen peroxide (H 2 O 2 ) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

1 . An electronic device, comprising: 
 a semiconductive substrate;    a patterned dielectric layer disposed upon the semiconductive substrate including a plurality of openings in the patterned dielectric layer having at least a sidewall surface and a bottom surface;    a dielectric anti-reflective coating disposed on at least a portion of a top surface of the patterned dielectric layer;    a conductive material disposed on substantially the entirety of the bottom surface and at least a majority of the at least one sidewall surface of the plurality of openings in the dielectric layer;    a conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer; and    a patterned conductive material at least connected to a top surface of the conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer.    
   
   
       2 . The electronic device of  claim 1 , wherein the openings in the dielectric layer expose portions of the semiconductive substrate.  
   
   
       3 . The electronic device of  claim 2 , wherein the exposed portions of the semiconductive substrate include a metal silicide layer substantially covering the entirety of the exposed portion of the semiconductive substrate at the bottom surface of the plurality of openings in the dielectric layer.  
   
   
       4 . The electronic device of  claim 1 , wherein the conductive material includes titanium.  
   
   
       5 . The electronic device of  claim 1 , further comprising an adhesion promoting layer disposed upon substantially all of the conductive material.  
   
   
       6 . The electronic device of  claim 5 , wherein the adhesion promoting layer includes titanium nitride.  
   
   
       7 . The electronic device of  claim 1 , wherein the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer comprises tungsten.  
   
   
       8 . The electronic device of  claim 1 , wherein the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer ends at a location below a top surface of the patterned dielectric layer.  
   
   
       9 . The electronic device of  claim 1 , wherein the dielectric anti-reflective coating is substantially totally removed after the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer is formed.  
   
   
       10 . The electronic device of  claim 1 , further comprising a dielectric layer disposed over the patterned conductive material.  
   
   
       11 . A semiconductor die, comprising: 
 an integrated circuit supported by a base layer and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit device has a semiconductor structure with a patterned dielectric layer disposed above the base layer including a plurality of openings in the patterned dielectric layer having at least a sidewall surface and a bottom surface exposing portions of the semiconductive substrate;    a conductive material disposed on substantially the entirety of the bottom surface and at least a majority of the at least one sidewall surface of the plurality of openings in the dielectric layer;    a conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer; and    a patterned conductive material at least connected to a top surface of the conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer.    
   
   
       12 . The semiconductor die of  claim 11 , wherein the openings in the dielectric layer comprise at least one an electrical contact to of a plurality of diffused regions in the base layer, and a conductive gate disposed between adjacent ones of the plurality of diffused regions.  
   
   
       13 . The semiconductor die of  claim 11 , wherein the exposed portions of the semiconductive substrate include a metal silicide layer substantially covering the entirety of the exposed portion of the semiconductive substrate at the bottom surface of the plurality of openings in the dielectric layer.  
   
   
       14 . The semiconductor die of  claim 11 , wherein the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer comprises tungsten up to a location below a top surface of the patterned dielectric layer.  
   
   
       15 . The semiconductor die of  claim 11 , further including a dielectric anti-reflective coating on a portion of a top surface of the patterned dielectric layer, and the dielectric anti-reflective coating is substantially totally removed after the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer is formed.  
   
   
       16 . A memory device, comprising: 
 an array of memory cells, wherein at least one memory cell has a bit-line contact including a patterned dielectric layer disposed upon a semiconductive substrate including a plurality of openings in the patterned dielectric layer having at least a sidewall surface and a bottom surface exposing portions of the semiconductive substrate;    a dielectric anti-reflective coating disposed on at least a portion of a top surface of the patterned dielectric layer;    a conductive material disposed on substantially the entirety of the bottom surface and at least a majority of the at least one sidewall surface of the plurality of openings in the dielectric layer;    a conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer; and    a patterned conductive material at least connected to a top surface of the conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer.    
   
   
       17 . The memory device of  claim 16 , wherein at least one of the at least one memory cell comprises a floating gate disposed between a control gate and the semiconductive substrate.  
   
   
       18 . The memory device of  claim 16 , wherein the exposed portions of the semiconductive substrate include a metal silicide layer substantially covering the entirety of the exposed portion of the semiconductive substrate at the bottom surface of the plurality of openings in the dielectric layer.  
   
   
       19 . The memory device of  claim 16 , wherein the conductive material includes titanium.  
   
   
       20 . The memory device of  claim 16 , further comprising an adhesion promoting layer disposed upon substantially all of the conductive material, wherein the adhesion promoting layer comprises titanium nitride.  
   
   
       21 . The memory device of  claim 16 , wherein the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer comprises tungsten.  
   
   
       22 . The memory device of  claim 16 , wherein the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer ends at a location below a top surface of the patterned dielectric layer.  
   
   
       23 . The memory device of  claim 16 , further comprising a dielectric layer disposed over the patterned conductive material.  
   
   
       24 . A memory module, comprising: 
 a support;    a plurality of leads extending form the support;    a command link coupled to at least one of the plurality of leads;    a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads;    at least one memory device contain on the support and coupled to the command link, including at least one memory cell having a contact including a patterned dielectric layer disposed upon a semiconductive substrate including a plurality of openings in the patterned dielectric layer having at least a sidewall surface and a bottom surface exposing portions of the semiconductive substrate;    a dielectric anti-reflective coating disposed on at least a portion of a top surface of the patterned dielectric layer;    a conductive material disposed on substantially the entirety of the bottom surface and at least a majority of the at least one sidewall surface of the plurality of openings in the dielectric layer;    a conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer; and    a patterned conductive material at least connected to a top surface of the conductive material substantially filling a remaining portion of the plurality of openings in the dielectric layer.    
   
   
       25 . The memory module of  claim 24 , wherein the memory device comprises at least one non-volatile memory cell.  
   
   
       26 . The memory module of  claim 24 , wherein the exposed portions of the semiconductive substrate include a metal silicide layer substantially covering the entirety of the exposed portion of the semiconductive substrate at the bottom surface of the plurality of openings in the dielectric layer.  
   
   
       27 . The memory module of  claim 24 , further comprising a titanium nitride layer disposed upon substantially all of the conductive material.  
   
   
       28 . The memory module of  claim 24 , wherein the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer comprises tungsten.  
   
   
       29 . The memory module of  claim 24 , wherein the conductive material substantially filling the remaining portion of the plurality of openings in the dielectric layer ends at a location below a top surface of the patterned dielectric layer.  
   
   
       30 . The memory module of  claim 24 , further comprising a dielectric layer disposed over the patterned conductive material.