Nonvolatile memory device and method of forming same

Abstract

In a method of forming a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device, a plurality of first gates may be formed on a semiconductor substrate. A plurality of charge storage spacers may be formed on the plurality of first gates so that a given charge storage spacer may be disposed on a sidewall of a given first gate. A plurality of second gates may be disposed on the plurality of first gates so that a given second gate is on a sidewall of a given first gate and covers a given charge storage spacer.

1 .- 14 . (canceled)  
   
   
       15 . A silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory device, comprising: 
 a plurality of first gates disposed on a given region of a semiconductor substrate;    a plurality of charge storage spacers disposed on the plurality of first gates so that a given charge storage spacer is on a sidewall of a given first gate; and    a plurality of second gates disposed on the plurality of first gates so that a given second gate is on a sidewall of a given first gate and covers a given charge storage spacer.    
   
   
       16 . The device of  claim 15 , further comprising: 
 a plurality of device isolating layers defining an active region disposed in a given region of the semiconductor substrate, wherein the device isolating layers are two-dimensionally disposed along columns and rows.    
   
   
       17 . The device of  claim 16 , wherein 
 the plurality of first gates cross over the plurality of device isolating layers and are parallel to each other, and    a given pair of first gates are disposed on each of the device isolating layers.    
   
   
       18 . The device of  claim 17 , wherein 
 the charge storage spacers are disposed on internal sidewalls of an adjoining two first gates, and    each first gate of the adjoining two first gates crosses over a different device isolating layer.    
   
   
       19 . The device of  claim 18 , further comprising: 
 an impurity region disposed between a given pair of charge storage spacers that are disposed on the internal sidewalls of the adjoining two first gates, wherein the impurity region represents a common source line of adjoining cell transistors.    
   
   
       20 . The device of  claim 17 , further comprising: 
 an impurity region disposed between a given pair of first gates crossing over the same device isolating layer, wherein the impurity region is divided by the device isolating layer.    
   
   
       21 . The device of  claim 20 , further comprising: 
 a plurality of insulating spacers disposed adjacent to the impurity region, each insulating spacer disposed on another sidewall of a given first gate opposite to the sidewall on which a given charge storage spacer is disposed.    
   
   
       22 . The device of  claim 20 , further comprising: 
 a material pattern disposed adjacent to the impurity region and on another sidewall of a given first gate opposite to the sidewall on which a given charge storage spacer is disposed, wherein the material pattern is formed of an material substantially identical to a material of the second gate.    
   
   
       23 . The device of  claim 15 , wherein the first gates and second gates are composed of at least one material selected from a group comprising polysilicon, silicide and metal.  
   
   
       24 . The device of  claim 15 , wherein the plurality of charge storage spacers are formed of silicon nitride or silicon oxynitride.  
   
   
       25 . The device of  claim 16 , wherein each of the charge storage spacers includes a sidewall that is formed on a device isolating layer to isolate a charge storage spacer from another charge storage spacer.  
   
   
       26 . The device of  claim 15 , further comprising: 
 a gate insulating layer interposed between the first gates, second gates, charge storage spacers and semiconductor substrate;    a first insulating layer interposed between the plurality of first gates and the plurality of charge storage spacers;    a second insulating layer interposed between the plurality of charge storage spacers and the plurality of second gates; and    a connector connecting the first gates and second gates, wherein the gate insulating layer and the first insulating layer are composed of silicon oxide.