Alignment of instructions and replies across multiple devices in a cascaded system, using buffers of programmable depths

Abstract

Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

1 - 22 . (canceled)  
   
   
       23 . A method for aligning request and reply signals between devices in a system of cascaded devices, said method comprising the steps of: 
 receiving and outputting a request signal at a first device;    receiving a first reply signal at said first device;    generating a second reply signal at said first device in response to operations performed in response to said request signal and in response to said first reply signal;    outputting said second reply signal;    buffering said request signal if a second device coupled downstream from said first device has a lower latency than said first device; and    buffering said second reply signal if said second device coupled downstream from said first device has a higher latency than said first device.    
   
   
       24 . The method of  claim 23 , wherein said first device and said second device are content addressable memory (CAM) devices.  
   
   
       25 . The method of  claim 24 , wherein said operations performed include a search operation.  
   
   
       26 . The method of  claim 25 , wherein said first device inserts a search hit index into said second reply signal.  
   
   
       27 . The method of  claim 24 , wherein said request signal originates from a host ASIC device.  
   
   
       28 - 46 . (canceled)  
   
   
       47 . A router, comprising: 
 a first device having a first latency;    a second device having a second latency different from said first latency; and    at least one buffer coupled between outputs of said first device and inputs of said second device, said at least one buffer being programmed to transfer signals on the outputs to the inputs by substantially equating said first and said second latencies.    
   
   
       48 . The router of  claim 47 , wherein said first device and said second device are content addressable memory (CAM) devices.  
   
   
       49 . The router of  claim 47 , wherein said first device receives a request signal and a first reply signal.  
   
   
       50 . The router of  claim 49 , wherein said first device generates a second reply signal from operations performed in response to said request signal and from said first reply signal.  
   
   
       51 . The router of  claim 50 , wherein said first device and said second device are content addressable memory (CAM) devices.  
   
   
       52 . The router of  claim 51 , wherein said operations performed include a search operation.  
   
   
       53 . The router of  claim 52 , wherein said first device inserts a search hit index into said second reply signal.  
   
   
       54 . The router of  claim 51 , wherein said request signal originates from a host ASIC device.  
   
   
       55 - 62 . (canceled)