Alignment of instructions and replies across multiple devices in a cascaded system, using buffers of programmable depths

Abstract

Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

1 - 33 . (canceled)  
   
   
       34 . A processor system, comprising: 
 a first device having a first input for receiving a request signal, a second input for receiving a first reply signal, a first output for outputting said request signal, and a second output for outputting a second reply signal, said second reply signal being generated from operations performed in response to said request signal and from said first reply signal;    at least one buffer coupled to said first device for receiving and outputting at least one of said outputted request signal and said second reply signal, said at least one buffer having an associated latency; and    a second device coupled to receive said outputted request signal and said second reply signal from said at least one buffer, said at least one buffer being configured to substantially equate a latency of said first device with a latency of said second device.    
   
   
       35 . The processor system of  claim 34 , wherein said first device and said second device are content addressable memory (CAM) devices.  
   
   
       36 . The processor system of  claim 35 , wherein said operations performed include a search operation.  
   
   
       37 . The processor system of  claim 36 , wherein said first device inserts a search hit index into said second reply signal.  
   
   
       38 . The processor system of  claim 35 , wherein said request signal originates from a host ASIC device.  
   
   
       39 . A processor system, comprising: 
 a first device having a first latency;    a second device having a second latency different from said first latency; and    at least one buffer coupled between outputs of said first device and inputs of said second device, said at least one buffer being programmed to transfer signals on the outputs to the inputs by substantially equating said first and said second latencies.    
   
   
       40 . The processor of system  claim 39 , wherein said first device and said second device are content addressable memory (CAM) devices.  
   
   
       41 . The processor of system  claim 39 , wherein said first device receives a request signal and a first reply signal.  
   
   
       42 . The processor of system  claim 41 , wherein said first device generates a second reply signal from operations performed in response to said request signal and from said first reply signal.  
   
   
       43 . The processor of system  claim 42 , wherein said first device and said second device are content addressable memory (CAM) devices.  
   
   
       44 . The processor system of  claim 43 , wherein said operations performed include a search operation.  
   
   
       45 . The processor system of  claim 44 , wherein said first device inserts a search hit index into said second reply signal.  
   
   
       46 . The processor system of  claim 43 , wherein said request signal originates from a host ASIC device.  
   
   
       47 - 62 . (canceled)