Asynchronous system-on-a-chip interconnect

Abstract

Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.

1 . An integrated circuit, comprising: 
 a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates;    a plurality of clock domain converters, each clock domain converter being coupled to a corresponding one of the synchronous modules, and being operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol; and    an asynchronous crossbar coupled to the plurality of clock domain converters, and operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.    
   
   
       2 . The integrated circuit of  claim 1  wherein the asynchronous crossbar is operable to route the data from any of a first number of input channels to any of a second number of output channels according to routing control information, each combination of an input channel and an output channel comprising one of a plurality of links, the crossbar being operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information, wherein events on different links are uncorrelated.  
   
   
       3 . The integrated circuit of  claim 2  wherein the crossbar is operable to transfer the data on at least one of the links based on at least one timing assumption.  
   
   
       4 . The integrated circuit of  claim 3  wherein the at least one timing assumption comprises any of a pulse timing assumption, an interference timing assumption, and an implied-data-neutrality timing assumption.  
   
   
       5 . The integrated circuit of  claim 1  wherein the asynchronous handshake protocol between a first sender and a first receiver comprises: 
 the first sender sets a data signal valid when an enable signal from the first receiver goes high;    the first receiver lowers the enable signal upon receiving the valid data signal;    the first sender sets the data signal neutral upon receiving the low enable signal; and    the first receiver raises the enable signal upon receiving the neutral data signal.    
   
   
       6 . The integrated circuit of  claim 1  wherein the asynchronous handshake protocol is delay-insensitive.  
   
   
       7 . The integrated circuit of  claim 1  further comprising at least one repeater, each repeater being coupled between a selected one of the clock domain converters and the asynchronous crossbar.  
   
   
       8 . The integrated circuit of  claim 7  wherein each repeater comprises an asynchronous half-buffer circuit.  
   
   
       9 . The integrated circuit of  claim 1  wherein the asynchronous crossbar is operable to arbitrate among multiple requests corresponding to a same destination synchronous module.  
   
   
       10 . The integrated circuit of  claim 9  wherein the asynchronous crossbar comprises arbitration circuitry to effect arbitration, the arbitration circuitry comprising at least one Seitz arbiter.  
   
   
       11 . The integrated circuit of  claim 1  further comprising a rate throttling circuit associated with a specific one of the synchronous modules which is operable to control transmission of the data to the corresponding clock domain converter.  
   
   
       12 . The integrated circuit of  claim 11  wherein the rate throttling circuit is operable to control transmission of the data by delaying transmission of the data in accordance with a priority associated with the specific synchronous module.  
   
   
       13 . The integrated circuit of  claim 11  wherein the rate throttling circuit is operable to control transmission of the data in response to congestion between the corresponding clock domain converter and the asynchronous crossbar.  
   
   
       14 . The integrated circuit of  claim 13  wherein the rate throttling circuit is operable to determine the congestion with reference to the asynchronous handshake protocol between the corresponding clock domain converter and the asynchronous crossbar.  
   
   
       15 . The integrated circuit of  claim 1  further comprising a built-in-self-test (BIST) module between one of the clock domain converters and the asynchronous crossbar, the BIST module being operable to transmit test vectors to and receive result vectors from each of the synchronous modules via the asynchronous crossbar.  
   
   
       16 . The integrated circuit of  claim 15  wherein the BIST module comprises a scan register for receiving the test vectors from external test equipment.  
   
   
       17 . The integrated circuit of  claim 15  wherein the BIST module is operable to transmit a first test vector to a first one of the synchronous modules via the asynchronous crossbar, the first synchronous module being operable to transmit a first result vector corresponding to the first test vector to a second one of the synchronous modules via the asynchronous crossbar, the second synchronous module being operable to transmit a second result vector to the BIST module via the asynchronous crossbar, the BIST module being further operable to verify the second result vector.  
   
   
       18 . The integrated circuit of  claim 1  wherein the integrated circuit comprises a multi-processor system, the plurality of synchronous modules comprising at least two central processing units with associated cache memory, at least one memory controller, at least one internal peripheral device, and at least one I/O interface.  
   
   
       19 . The integrated circuit of  claim 18  further comprising at least one repeater, each repeater being coupled between a selected one of the clock domain converters and the asynchronous crossbar.  
   
   
       20 . The integrated circuit of  claim 1  wherein the integrated circuit comprises a synchronous optical network (SONET) interconnect switch, the plurality of synchronous modules comprising a plurality of SONET interfaces.  
   
   
       21 . The integrated circuit of  claim 20  further comprising at least one repeater, each repeater being coupled between a selected one of the clock domain converters and the asynchronous crossbar.  
   
   
       22 . At least one computer-readable medium having data structures stored therein representative of the integrated circuit of  claim 1 .  
   
   
       23 . The at least one computer-readable medium of  claim 22  wherein the data structures comprise a simulatable representation of the integrated circuit.  
   
   
       24 . The at least one computer-readable medium of  claim 23  wherein the simulatable representation comprises a netlist.  
   
   
       25 . The at least one computer-readable medium of  claim 22  wherein the data structures comprise a code description of the integrated circuit.  
   
   
       26 . The at least one computer-readable medium of  claim 25  wherein the code description corresponds to a hardware description language.  
   
   
       27 . A set of semiconductor processing masks representing the integrated circuit of  claim 1.