Display device

Abstract

The present invention, in a display device which includes a SRAM, prevents a phenomenon that power source fluctuation and display timings are not synchronized and hence, flickering occurs on a display surface of a liquid crystal panel. A display device includes a display panel having a plurality of pixels and scanning lines which apply a scanning voltage to the plurality of pixels; and a drive circuit which supplies a scanning voltage to the scanning lines, wherein the drive circuit includes a first booster circuit which generates a first voltage by elevating a reference voltage, a regulator which regulates the first voltage, and a second booster circuit which generates a second voltage by elevating a voltage outputted from the regulator. The second booster circuit generates the second voltage (selective scanning voltage) and a third voltage (non-selective scanning voltage). When video data is inputted from the outside based on an RGB interface, the second booster circuit is operated in response to an external clock.

1 . A display device comprising: 
 a display panel having a plurality of pixels and scanning lines which apply a scanning voltage to the plurality of pixels; and    a drive circuit which supplies a scanning voltage to the scanning lines, wherein    the drive circuit includes    a first booster circuit which generates a first voltage by elevating a reference voltage,    a regulator which regulates the first voltage, and    a second booster circuit which generates a second voltage by elevating a voltage outputted from the regulator.    
   
   
       2 . A display device according to  claim 1 , wherein the second booster circuit generates the second voltage and a third voltage.  
   
   
       3 . A display device according to  claim 2 , wherein the second voltage is a selective scanning voltage which is applied to the plurality of pixels via the scanning lines, and 
 the third voltage is a non-selective scanning voltage which is applied to the plurality of pixels via the scanning lines.    
   
   
       4 . A display device according to any one of  claims 1  to  3 , wherein the display device includes a clock generating circuit which generates an inner clock, 
 the first booster circuit is operated in response to the inner clock, and    the second booster circuit is operated in response to the inner clock or an external clock which synchronizes with a control signal inputted from the outside.    
   
   
       5 . A display device according to  claim 4 , wherein when video data is inputted from the outside based on a RGB interface, the second booster circuit is operated in response to the external clock.  
   
   
       6 . A display device comprising: 
 a drive circuit to which video data is supplied from the outside; video lines to which a video signal which the drive circuit outputs is supplied; and    pixels to which the video signal is supplied via the video lines, wherein    the drive circuit includes    a SRAM which stores the video data and a memory control means,    the SRAM is divided into a plurality of mats, and    the memory control means makes precharge start timings to bit lines for respective mats different from each other at the time of reading the video data from the SRAM.    
   
   
       7 . A display device comprising: 
 a drive circuit to which video data is supplied from the outside; video lines to which a video signal which the drive circuit outputs is supplied; and    pixels to which the video signal is supplied via the video lines, wherein    the drive circuit includes a SRAM which stores the video data and a memory control means,    the SRAM is divided into a plurality of mats,    the plurality of mats are divided into groups, and    the memory control means makes precharge start timings to bit lines for respective mats of each group different from each other at the time of reading the video data from the SRAM.    
   
   
       8 . A display device comprising: 
 a drive circuit to which video data is supplied from the outside; video lines to which a video signal which the drive circuit outputs is supplied; and    pixels to which the video signal is supplied via the video lines, wherein    the drive circuit includes    a SRAM which stores the video data and a memory control means,    the SRAM is divided into a plurality of mats, and    the memory control means performs precharging with respect to the bit lines of the mats which include memory cells to which the video data is written and does not perform the precharging with respect to the bit lines of the mats except for the mats which include memory cells to which the video data is written at the time of writing the video data into the SRAM.    
   
   
       9 . A display device comprising: 
 a drive circuit to which video data is supplied from the outside; video lines to which a video signal which the drive circuit outputs is supplied; and    pixels to which the video signal is supplied via the video lines, wherein    the drive circuit includes a SRAM which stores the video data and a memory control means, and    the memory control means determines that, when the display device assumes a partial display state, cells which store data of 1 bit among display data of n bits are valid and cells which store data of other (n−1) bits are invalid.    
   
   
       10 . A display de-vice according to  claim 9 , wherein the SRAM includes a means  1  which applies a first reference voltage or second reference voltage to the bit lines to which the cells which are determined invalid are connected in a partial display state.  
   
   
       11 . A display device according to  claim 9  or  10 , wherein the SRAM includes a means  2  which prohibits the data writing to the invalid cells in the partial display state.  
   
   
       12 . A display device according to  claim 10  or  claim 11 , wherein the written data to the invalid cell is data which forms the voltage of the bit lines which are connected to the invalid cells into the voltage which is applied to the means  1 .