US2006237804A1PendingUtilityA1

Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films

Individually held — no corporate assignee on recordPriority: Dec 30, 2003Filed: Jun 22, 2006Published: Oct 26, 2006
Est. expiryDec 30, 2023(expired)· nominal 20-yr term from priority
H10P 10/00H10D 30/791H10D 64/017
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Claims

Abstract

The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

Claims

exact text as granted — not AI-modified
1 . A transistor formed on a substrate comprising: 
 a metal gate electrode;    sidewall spacers formed on the sides of the metal gate electrode;    a nitride etch stop layer disposed over the metal gate electrode and sidewall spacers, that creates stress in the underlying transistor structure; and    an inter-level dielectric layer formed over the sidewall spacers, the metal gate electrode, and nitride etch stop layer.    
   
   
       2 . The transistor of  claim 1  wherein the metal gate electrode comprises a material or materials from the group consisting of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), titanium (TiN, TiC) and tantalum (TaN, TaC).  
   
   
       3 . The transistor of  claim 1  wherein the metal gate electrode comprises multiple metals.  
   
   
       4 . A method comprising: 
 forming a sacrificial gate electrode over a substrate;    forming sidewall spacers on the sides of the sacrificial gate electrode, wherein the sidewall spacers are selected from the group consisting of silicon nitride or carbon doped nitride;    forming a sacrificial inter-level dielectric layer, wherein the sacrificial inter-level dielectric layer comprises a soft chemical vapor deposition oxide;    removing the sacrificial gate electrode;    depositing a replacement gate electrode;    polishing the sacrificial inter-level dielectric layer and the replacement gate electrode; and    performing a wet etch removal on the sacrificial inter-level dielectric layer.    
   
   
       5 . The method of  claim 4 , wherein said etch removal utilizes a buffered hydrofluoric acid (HF) and an ethylene glycol.

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