Apparatus to improve bandwidth for circuits having multiple memory controllers

Abstract

An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller. The second busy write output signal indicates when the second memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the second memory controller.

1 . A system comprising: 
 an address bus and a data bus, a memory controller electrically communicating with said address bus and said data bus;    a first output signal circuit electronically communication with the memory controller wherein said first output circuit has means for signaling when the memory controller releases the address bus; and    a second output signal circuit electrically communicating with the memory controller wherein said second output signal circuit has means for signaling when the memory controller releases the data bus.    
   
   
       2 . The apparatus of  claim 1  further comprising: 
 a first input signal circuit electrically communicating with said memory controller, wherein said first input signal circuit has means for signaling when said address bus is released by an external memory controller for an access by said memory controller; and    a second input circuit electrically communicating with the said memory controller, wherein said second input signal circuit has mean for signaling when said data bus is released by said external memory controller for a access by said memory controller.    
   
   
       3 . The apparatus of  claim 2  wherein said memory controller has means for delaying all external accesses to said data bus subsequent to an initial access to said data bus by using the second input signal.  
   
   
       4 . The apparatus of  claim 2  wherein said memory controller further comprising means for anticipating a next external access by using to said address bus subsequent to an initial access to said data bus by using the first input signal.  
   
   
       5 . A system for improving bandwidth among a plurality of memory controllers, said system comprising: 
 a first memory controller electrically communicating with an external data and address bus for controlling a first memory circuit;    a second memory controller electrically communicating with an external data and address bus for controlling a second memory circuit;    a first output signal circuit electrically communicating with the first memory controller, wherein said first output signal has means for signaling when the said first memory controller releases said address bus for a next external access subsequent to an access to said data bus by said first memory controller;    a second output signal circuit electrically communicating with the first memory controller, wherein said second output has mean for signaling when the said first memory controller releases said data bus for a next external subsequent to an access to said data bus by said first memory controller;    a first output signal circuit electrically communicating with the second memory controller, wherein said first output signal has means for signaling when the said second memory controller releases said address bus for a next external access subsequent to an access to said data bus by said second memory controller; and    a second output signal circuit electrically communicating with the second memory controller, wherein said second output has means for signaling when the said second memory controller releases said data bus for a next external access subsequent to an access to said data bus by said second memory controller.    
   
   
       6 . The apparatus of  claim 5  further comprising: 
 a first input signal circuit electrically communicating with the said first memory controller, wherein said first input signal has means for signaling when said external address bus is released for a next access by said first memory controller;    a second input signal circuit electrically communicating with the said first memory controller, wherein said second input signal has means for signaling when said external data bus is released for a next access by said first memory controller;    a first input signal circuit electrically communicating with the said second memory controller, wherein said first input signal has means for signaling when said external address bus is released for a next access by said second memory controller; and    a second input signal circuit electrically communicating with the said second memory controller, wherein said second input signal has means for signaling when said external data bus is released for a next access by said second memory controller.    
   
   
       7 . The apparatus of  claim 5  wherein said first memory controller further comprising: 
 a memory controller selected from the group consisting of: a static ram memory controller, a flash memory controller, a burst flash memory controller, a single data rate synchronous dynamic random access memory (SDR SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a pseudo-static random access memory (PSRAM), a CellularRam, and a reduced latency dynamic random access memory (RLDRAM).    
   
   
       8 . The apparatus of  claim 5  wherein said second memory controller further comprising: 
 a memory controller selected from the group consisting of: a static ram memory controller, a flash memory controller, a burst flash memory controller, a single data rate synchronous dynamic random access memory (SDR SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a pseudo-static random access memory (PSRAM), a CellularRam, and a reduced latency dynamic random access memory (RLDRAM).    
   
   
       9 . The apparatus of  claim 5  wherein said first memory controller has means for signaling that the external data bus is released for external access to said external bus subsequent to an initial write by asserting a busy_write_out signal.  
   
   
       10 . The apparatus of  claim 9  wherein said first memory controller further includes a store element means for holding a set of data including a first integer number of clock cycles, wherein a write transfer from said external data bus is completed within said busy_write_out signal is asserted to indicate that said current write access to said external data bus needs said first integer number of clock cycles to be completed.  
   
   
       11 . The apparatus of  claim 5  wherein said second memory controller has means for signaling that the external data bus is released for external access to said external bus subsequent to an initial write by asserting a busy_write_out signal.  
   
   
       12 . The apparatus of  claim 9  wherein said second memory controller further includes a store element means for holding a set of data including a first integer number of clock cycles, wherein a write transfer from said external data bus is completed within said busy_write_out signal is asserted to indicate that said current write access to said external data bus needs said first integer number of clock cycles to be completed.  
   
   
       13 . The apparatus of  claim 5  wherein said first memory controller has means for signaling that the address bus is released to anticipate a next external access to said data bus subsequent to an initial read access to said external data by said first memory controller by asserting a busy_read_out signal.  
   
   
       14 . The apparatus of  claim 13  wherein said first memory controller has mean for asserting said busy_read_out signal during the time period when a set of data floats (TDF) at said data bus.  
   
   
       15 . The apparatus of  claim 5  wherein said second memory controller has means for signaling that the address bus is released to anticipate a next external access to said data bus subsequent to an initial read access to said external data bus by said second memory controller by asserting a busy_read_out signal.  
   
   
       16 . The apparatus of  claim 15  wherein said second memory controller has means for asserting said busy_read_out signal during the time period when a set of data floats (TDF) at said data bus.  
   
   
       17 . The apparatus of  claim 6  wherein said first memory controller is electrically communicating with said second memory controller, and wherein said first memory controller's busy_write_out signal drives second memory controller's busy_write_in signal.  
   
   
       18 . The apparatus of  claim 6  wherein said first memory controller is electrically communicating with said second memory controller, and wherein said second memory controller's busy_write_out signal drives first memory controller's busy_write_in signal.  
   
   
       19 . The apparatus of  claim 6  wherein said first memory controller is electrically communicating with said second memory controller, and wherein said first memory controller's busy_read_out signal drives second memory controller's busy_read_in signal.  
   
   
       20 . The apparatus of  claim 6  wherein said first memory controller is electrically communicating with said second memory controller, and wherein said second memory controller's busy_read_out signal drives first memory controller's busy_read_in signal.  
   
   
       21 . The method of improving bandwidth for circuits having a plurality of memory controllers, said method comprising the steps of: 
 a) asserting a first output signal to indicate when a first memory controller releases an address bus for a next external access subsequent to an access to said data bus by said first memory controller;    b) asserting a second output signal to indicate when said first memory controller releases an said data bus for a next external access subsequent to an access to said data bus by said first memory controller;    c) asserting a first output signal to indicate when a second memory controller releases said address bus for a next external access subsequent to an access to said data bus by said second memory controller; and    d) asserting a second output signal to indicate when said second memory controller releases an said data bus for a next external access subsequent to an access to said data bus by said second memory controller.    
   
   
       22 . The method of  claim 21  further comprising the steps of: 
 e) asserting a first input signal to indicate when said external address bus is released for an access by said first memory controller;    f) asserting a second input signal to indicate when said external data bus is released for an access by said controller;    g) asserting a first input signal to indicate when said external address bus is released for an access by said second memory controller; and    h) asserting a second input signal to indicate when said external data bus is released for an access by said first memory controller.    
   
   
       23 . The method of  claim 21  wherein said step a) of asserting said first output signal further includes the step of: 
 a) asserting a signal indicating said address bus is released to anticipate a next external access to said data bus subsequent an initial access to said external data bus by said first memory controller.    
   
   
       24 . The method of  claim 21  wherein said step b) of asserting said second output signal further includes the step of: 
 b) asserting a signal to indicate delay all external accesses to said external data bus subsequent to an initial access to said external data bus said first memory controller are not allowed.    
   
   
       25 . The method of  claim 21  wherein said step c) of asserting said first output signal further includes the step of: 
 c) asserting a signal indicating said address bus is released to anticipate a next external access to said data bus subsequent an initial access to said external data bus by said second memory controller.    
   
   
       26 . The method of  claim 21  wherein said step d) of asserting said second output signal further includes the step of: 
 d) asserting a signal to indicate delay all external accesses to said external data bus subsequent to an initial access to said external data bus said second memory controller are not allowed.