A method of forming semiconductor structures
Abstract
In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
Claims
exact text as granted — not AI-modified1 - 48 . (canceled)
49 . A method of forming a semiconductor structure comprising:
providing a semiconductive substrate; proving a first masking layer over the semiconductive substrate; providing a second masking layer over the first masking layer, the second masking layer comprising a first upper surface and having a first thickness between the first masking layer and the first upper surface; forming an opening through the first and second masking layers and partially into the semiconductive substrate; removing substantially an entirety of the first upper surface of the second masking layer to form a second upper surface and to reduce the first thickness to a smaller second thickness of the second masking layer; and with the second thickness of the second masking layer remaining, removing a portion of the first masking layer.
50 . The method of claim 49 wherein the second thickness comprises at least about 600 angstroms.
51 . The method of claim 49 wherein the first masking layer is substantially unchanged during the removing of the first upper surface of the second masking layer.
52 . The method of claim 49 wherein the removing of the first upper surface of the second masking layer comprises etching the second masking layer with a phosphoric acid.
53 . The method of claim 49 wherein the removing of the first upper surface of the second masking layer comprises etching the second masking layer at a rate of about 55 Angstroms per minute.
54 . The method of claim 49 wherein the removing of the first upper surface of the second masking layer comprises etching from about 50 Angstroms to about 250 Angstroms of the second masking layer.
55 . The method of claim 49 wherein the forming of the opening comprises forming a periphery of the opening having sidewalls of the first and second masking layers and having sidewalls of the semiconductive substrate, and wherein the sidewalls of the semiconductive substrate are aligned with the sidewalls of the first and second masking layers.
56 . The method of claim 49 wherein the second masking layer comprises silicon nitride.
57 . The method of claim 49 wherein the first masking layer comprises silicon oxide.
58 . The method of claim 49 wherein the forming of the opening comprises forming a periphery of the opening having at least sidewalls of the second masking layer, and wherein the removing of the first upper surface of the second masking layer further comprises removing the sidewalls to laterally space the second masking layer from the periphery of the opening.
59 . A method of forming a semiconductor structure comprising:
providing a semiconductive substrate; proving a first masking layer over the semiconductive substrate; providing a second masking layer over the first masking layer; forming an opening through the first and second masking layers and partially into the semiconductive substrate, the opening having a periphery comprising the first masking layer and the second masking layer; after the forming of the opening and in a first recessing step, laterally recessing the second masking layer to leave the second masking layer laterally spaced from the periphery; and after the first recessing step, laterally recessing the first masking layer to leave the first masking layer laterally spaced from the periphery, the first masking layer being spaced a greater distance from the periphery than the second masking layer.
60 . The method of claim 59 wherein the recessing of the first masking layer comprises etching the first masking layer with a hydrofluoric acid.
61 . The method of claim 59 wherein the first masking layer comprises an oxide.
62 . The method of claim 59 wherein the second masking layer comprises a nitride.
63 . The method of claim 59 wherein the recessing of the first masking layer comprises leaving the second masking layer substantially unchanged.
64 . The method of claim 59 wherein the periphery of the opening comprises sidewalls of the semiconductive substrate and sidewalls of the first and second masking layers, and wherein the sidewalls of the semiconductive substrate are aligned with the sidewalls of the first and second masking layers.
65 . The method of claim 59 further comprising oxidizing the semiconductive substrate to form an oxide layer partially filling the opening in the semiconductive substrate.
66 . The method of claim 59 further comprising oxidizing the semiconductive substrate to form an oxide layer partially filling the opening in the semiconductive substrate, the oxide layer extending from the first masking layer.Join the waitlist — get patent alerts
Track US2006234469A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.