Semiconductor device with FinFET and method of fabricating the same

Abstract

A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided,

1 . A semiconductor device comprising: 
 an active region formed of a semiconductor substrate and projecting from a surface of the substrate;    a fin having a first projection and a second projection composed of the active region arranged in parallel and at each side of a central trench formed in a central portion of the active region, upper surfaces and side surfaces of the first projection and the second projection comprising a channel region;    a channel ion implantation layer at a bottom of the central trench and at a lower portion of the fin;    a gate oxide layer on the fin;    a gate electrode on the gate oxide layer; and    a source region and a drain region in the active region at sides of the gate electrode.    
   
   
       2 . The semiconductor device of  claim 1 , further comprising a threshold voltage controlling ion implantation layer formed by doping the fin with an impurity of a conductivity type opposite to a conductivity type of an impurity used to dope the channel ion implantation layer, and formed at an upper portion of the fin in the first projection and the second projection.  
   
   
       3 . The semiconductor device of  claim 1 , further comprising a device isolating layer about the active region at lower side surfaces of the first projection and the second projection.  
   
   
       4 . The semiconductor device of  claim 1 , wherein a width of the gate electrode is equal to or greater than that of the central trench and wherein the gate extends to cover the upper surfaces and the side surfaces of the first projection and the second projection.  
   
   
       5 . A method of fabricating a semiconductor device comprising: 
 forming a dummy gate extending on an active region of a semiconductor substrate;    providing a shielding layer on the dummy gate, and planarizing the shielding layer using the dummy gate as an end point of planarization;    selectively removing the dummy gate with respect to the shielding layer;    performing local channel ion implantation to form a channel ion implantation layer within the active region using the shielding layer as an ion implantation mask;    etching the semiconductor substrate using the shielding layer as an etch mask to form a central trench that exposes the channel ion implantation layer;    recessing the shielding layer;    depositing a gate oxide layer in the central trench;    forming a gate electrode on the gate oxide layer; and    forming a source region and a drain region in the active region at both sides of the gate electrode.    
   
   
       6 . The method of  claim 5 , wherein a height of the dummy gate is equal to or greater than depths of the source region and the drain region.  
   
   
       7 . The method of  claim 5 , after forming the channel ion implantation layer, further comprising: 
 doping an impurity of a conductivity type opposite that of an impurity of the channel ion implantation layer into an upper portion of the active region to form a threshold voltage controlling ion implantation layer.    
   
   
       8 . A method of fabricating a semiconductor device comprising: 
 forming an active region hard mask on a semiconductor substrate;    etching the substrate using the active region hard mask as an etch mask to define an active region projecting from a surface of the substrate and to form a trench encircling the active region;    isotropically etching the active region hard mask to form a hard mask pattern that exposes a top perimeter of the active region;    filling the trench with a gap fill oxide layer, and planarizing the gap fill oxide layer using the hard mask pattern as an end point of planarization;    forming a line type mask extending on the gap fill oxide layer and the hard mask pattern;    patterning the gap fill oxide layer and the hard mask pattern using the line type mask as an etch mask to form a dummy pattern including at least one channel region defining pattern in a central portion thereof;    providing a shielding layer on the line type mask, and planarizing the shielding layer using the line type mask as an end point of planarization;    selectively removing the line type mask and the channel region defining pattern with respect to the shielding layer to form an opening that exposes a surface of the active region;    local channel ion implanting via the opening to form a channel ion implantation layer within the active region;    etching the active region under the opening to form a central trench in a portion of the active region including a fin channel at sides of the central trench;    recessing the shielding layer and the gap fill oxide layer to provide a device isolating layer about the active region, and exposing a fin channel that has a first projection and a second projection composed of a surface of the substrate arranged in parallel and at each side of the central trench between the central trench and the device isolating layer, the upper surface regions and side surface regions of the first projection and the second projection comprising a channel region;    forming a gate oxide layer on the fin;    forming a gate electrode on the gate oxide layer; and    forming a source region and a drain region in the active region at both sides of the gate electrodes.    
   
   
       9 . The method of  claim 8 , wherein a sum of a height of the line type mask and a height of the channel region defining pattern is equal to or greater than depths of the source and the drain.  
   
   
       10 . The method of  claim 8 , wherein in the forming of the channel ion implantation layer, the shielding layer is used as an ion implantation mask.  
   
   
       11 . The method of  claim 10 , wherein a doping energy of the local channel ion implanting is adjusted to allow impurities other than the impurities constituting the channel ion implantation layer to be doped entirely within the shielding layer or to be doped within the shielding layer and an upper surface of the active region.  
   
   
       12 . The method of  claim 8 , after forming the channel ion implantation layer, further comprising doping an impurity of a conductivity type opposite that of the impurity of the channel ion implantation layer into an upper portion of the active region to form a threshold voltage controlling ion implantation layer.  
   
   
       13 . The method of  claim 12 , wherein in the forming of the threshold voltage controlling ion implantation layer the shielding layer is used as an ion implantation mask.  
   
   
       14 . The method of  claim 13 , wherein a doping energy is adjusted to allow impurities other than the impurities constituting the threshold voltage controlling ion implantation layer to be doped within the shielding layer.  
   
   
       15 . The method of  claim 8 , wherein the active region hard mask comprises silicon nitride, and the isotropic etching is wet etching using H 3 PO 4 .  
   
   
       16 . The method of  claim 8 , wherein the isotropic etching is one of wet etching and dry etching using plasma.  
   
   
       17 . The method of  claim 8 , wherein the line type mask comprises silicon oxide nitride.  
   
   
       18 . The method of  claim 17 , wherein the shielding layer comprises silicon oxide.  
   
   
       19 . The method of  claim 8 , wherein the shielding layer comprises High Density Plasma-CVD oxide.  
   
   
       20 . The method of  claim 8 , wherein the device isolating layer is formed to have indented portions that expose side surfaces of the first projection and the second projection.