Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate

Abstract

The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.

1 . A semiconductor device comprising a first semiconductor chip and a second semiconductor chip, stacked atop a support substrate having an external connection terminal, the first semiconductor chip and the second semiconductor chip sealed in one package, 
 the first semiconductor chip being a memory chip and positioned at a lower layer,    and further, the second semiconductor chip being a logic chip and positioned at a layer above the first semiconductor chip.    
     
     
         2 . A semiconductor device comprising a first and a second semiconductor chips on which an alignment mark is formed for mutual alignment and which are stacked in one package, 
 the alignment mark being formed on a cover film formed on a chip surface.    
     
     
         3 . The semiconductor device as claimed in  claim 2 , wherein: 
 the alignment mark and a semiconductor chip pad are provided jointly.    
     
     
         4 . The semiconductor device as claimed in  claim 2 , wherein: 
 the alignment mark and a semiconductor chip pad are provided jointly, and    the pad is a non-bonding pad.    
     
     
         5 . The semiconductor device as claimed in  claim 2 , wherein: 
 an alignment mark provided on the first semiconductor chip and an alignment provided on the second semiconductor chip have an identical shape.    
     
     
         6 . A semiconductor device comprising a plurality of semiconductor chips stacked to be mounted in one package, 
 a cover film being formed at least on such a region of the semiconductor chip positioned at a lower layer as that on which rests the semiconductor chip positioned at an upper layer thereof.    
     
     
         7 . A semiconductor device comprising: 
 a plurality of semiconductor chips having a first function; and    a second semiconductor chip having a second function,    the first and second semiconductor chips being sealed in one package.    
     
     
         8 . The semiconductor device as claimed in  claim 7 , wherein: 
 the plurality of semiconductor chips having the first function and the second semiconductor chips are stacked in the package.    
     
     
         9 . The semiconductor device as claimed in  claim 7 , wherein: 
 the first function and the second function are different functions.    
     
     
         10 . The semiconductor device as claimed in  claim 7 , wherein: 
 the semiconductor chip having the first function is a memory chip and the semiconductor chip is a logic chip; and    power wiring and signal wiring being provided between the logic chip and an external connection terminal,    only power wiring being provided between the memory chip and the external connection terminal,    only signal wiring being provided between the memory chip and the logic chip.