US2006226515A1PendingUtilityA1

Semiconductor device and manufacturing method thereof

Assignee: SANYO ELECTRIC COPriority: Mar 13, 2001Filed: Jun 13, 2006Published: Oct 12, 2006
Est. expiryMar 13, 2021(expired)· nominal 20-yr term from priority
H10P 30/22H10W 20/435H10W 20/425H10B 99/00H10B 20/383H10B 20/00
50
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Claims

Abstract

A semiconductor device includes: a gate electrode on a semiconductor substrate through a gate insulated film; source/drain regions to be adjacent to said gate electrode; and an Al wiring through an interlayer insulating film covering said gate electrode, wherein impurity ions are implanted into a surface of said semiconductor substrate using as a mask said Al wiring, and a protection film is formed on the Al wiring so that the Al wiring is not exposed when said interlayer insulating film is etched.

Claims

exact text as granted — not AI-modified
1 - 7 . (canceled)  
   
   
       8 . A semiconductor device comprising: 
 a gate electrode on a semiconductor substrate through a gate insulated film;    source/drain regions to be adjacent to said gate electrode;    a narrow metallic wiring and a wide metallic wiring on an lower layer interlayer insulating film covering said gate electrode; and    an upper interlayer insulating film formed to cover said metallic wirings and flattened,    wherein a groove is formed in a surface of said wide metallic wiring.    
   
   
       9 . The semiconductor device according to  claim 8 , wherein impurity ions are implanted into a surface of said semiconductor substrate with said interlayer insulating films being etched by a prescribed amount using as a mask said metallic wirings and a photoresist formed thereabove.  
   
   
       10 . A semiconductor device according to  claim 8 , wherein slits are formed at regular intervals so as to subdivide said wide metallic wiring.  
   
   
       11 - 13 . (canceled)  
   
   
       14 . A semiconductor device comprising: 
 a semiconductor substrate;    a gate insulated film on the semiconductor substrate;    a gate electrode on the semiconductor substrate through the gate insulated film;    source/drain regions adjacent said gate electrode;    a lower interlayer insulating film covering said gate electrode;    a narrow metallic wiring and a wide metallic wiring on the lower interlayer insulating film covering said gate electrode; and    an upper interlayer insulating film formed to cover said metallic wirings,    wherein impurity ions are implanted into said semiconductor substrate with said interlayer insulating films being etched using said metallic wirings and a photoresist formed thereabove as masks, and a groove is formed on a surface of said wide metallic wiring.    
   
   
       15 . The semiconductor device of  claim 14 , wherein slits are formed on the device at regular intervals to subdivide said wide metallic wiring.  
   
   
       16 . The semiconductor device of  claim 14 , wherein said lower interlayer insulating film comprises layers of a first silicon oxide film, a silicon nitride film, a poly-Si film and a second silicon oxide film.  
   
   
       17 . A semiconductor device comprising: 
 a narrow metallic wiring;    a wide metallic wiring; and    a flattened interlayer insulating film formed so as to cover said narrow metallic wiring and said wide metallic wiring;    wherein a groove is formed on a surface of said wide metallic wiring.    
   
   
       18 . The semiconductor device according to  claim 17  further comprising a plurality of grooves formed at regular intervals so as to subdivide said wide metallic wiring.  
   
   
       19 . The semiconductor device according to  claim 18  wherein impurity ions are implanted into a surface of a semiconductor substrate in accordance with write information in a mask ROM.  
   
   
       20 . The semiconductor device according to  claim 19  wherein the narrow metallic wiring and the wide metallic wiring are formed so as to surround a region into which the impurity ions are implanted.  
   
   
       21 . The semiconductor device according to  claim 17  wherein impurity ions are implanted into a surface of a semiconductor substrate in accordance with write information in a mask ROM.  
   
   
       22 . The semiconductor device according to  claim 21  wherein the narrow metallic wiring and the wide metallic wiring are formed so as to surround a region into which the impurity ions are implanted.

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