Integrated circuit devices having buried insulation layers and methods of forming the same

Abstract

An integrated circuit device includes a gate electrode formed on an active region of an integrated circuit device and on a field isolation layer adjacent to the active region. A source region and a drain region are in the active region on alternate sides of the gate electrode. At least one buried insulation layer is beneath the drain region or the source region.

1 . An integrated circuit device comprising: 
 a field isolation layer on an integrated circuit substrate defining an active region;    a channel silicon layer in the active region;    a gate electrode on the field isolation layer adjacent to the active region;    a source region and a drain region in the channel silicon layer on alternate sides of the gate electrode; and    at least one buried insulation layer beneath the drain region or the source region, wherein the channel silicon layer covers the buried insulation layer, and a portion of the channel silicon layer contacts a portion of the integrated circuit substrate in the active region.    
   
   
       2 . An integrated circuit device according to  claim 1  wherein the channel silicon layer comprises epitaxially grown single crystalline silicon.  
   
   
       3 . An integrated circuit device according to  claim 1  wherein the gate electrode crosses top sides of the active region.  
   
   
       4 . An integrated circuit device according to  claim 3  wherein a top surface of the field isolation layer is lower than a top surface of the active region.  
   
   
       5 . An integrated circuit device according to  claim 3  wherein the gate electrode fills a groove at a boundary between the active region and the field isolation layer that exposes a top surface of the active region.  
   
   
       6 . An integrated circuit device according to  claim 5  further comprising: 
 a recessed liner layer beneath the field isolation layer, wherein inner sides of the groove include the top side of the active region and the top side of the field isolation layer adjacent to the top side of the active region and a bottom of the groove is defined by the recessed liner layer.    
   
   
       7 . An integrated circuit device according to  claim 1  wherein the buried insulation layer comprises a thermal oxide layer.  
   
   
       8 . An integrated circuit device according to  claim 1  wherein the buried insulation layer and the field isolation layer comprise the same material.  
   
   
       9 . An integrated circuit device according to  claim 1  wherein the buried insulation layer contacts a bottom surface of the drain region.  
   
   
       10 . An integrated circuit device according to  claim 1  wherein the buried insulation layer includes at least one vacancy.  
   
   
       11 . A method of fabricating an integrated device, comprising: 
 forming a field isolation layer on a substrate to define an active region;    forming a channel silicon layer in the active region;    forming a gate electrode on the active region and on the field isolation layer adjacent to the active region;    forming a source region and a drain region in the channel silicon layer on alternate sides of the gate electrode; and    forming at least one buried insulation layer beneath the drain region or the source region, wherein the channel silicon layer covers the buried insulation layer, and a portion of the channel silicon layer contacts a portion of the substrate in the active region.