Semiconductor device and method of manufacturing the same

Abstract

An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

1 . A semiconductor device comprising: 
 a semiconductor substrate of a first general conductivity type;    a semiconductor layer of the first general conductivity type disposed on a surface of the semiconductor substrate so as to provide a drain region;    two channel regions of a second general conductivity type disposed on the semiconductor layer;    an impurity region of the first general conductivity type disposed between the two channel regions, an junction interface between the impurity region and one of the channel regions being perpendicular to the surface of the semiconductor substrate;    an insulating film disposed on the impurity region;    a gate electrode disposed on the insulating film; and    a source region of the first general conductivity type formed in a surface of each of the channel regions.    
   
   
       2 . The semiconductor device of  claim 1 , wherein a bottom of the impurity region and a bottom of each of the channel regions are at a same level.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the gate electrode comprises a first gate electrode portion and a second gate electrode portion that are disposed on 
 the impurity region between the two channel regions, the first gate electrode portion is at least partially separated from the second gate electrode portion, and the first and second gate electrode portions are covered by another insulating film.    
   
   
       4 . The semiconductor device of  claim 3 , wherein a width of each of the first and second gate electrode portions is equal to or less than a depth of the channel regions.  
   
   
       5 . The semiconductor device of  claim 3 , wherein a ratio of a separation width between the first and second gate electrode portions to the depth of the channel region is 0.15 or smaller.  
   
   
       6 . The semiconductor device of  claim 1 , wherein the impurity region is configured to be pinched off by depletion regions extending from the channel regions when a the gate electrode and the source region are at a same electrical potential and a reverse bias voltage is applied between the source and drain regions.  
   
   
       7 . A method of manufacturing a semiconductor device, comprising: 
 providing a device intermediate comprising a semiconductor substrate of a first general conductivity type, a semiconductor layer of the first general conductivity type disposed on the semiconductor substrate and a first insulating film disposed on the semiconductor layer;    forming a gate electrode on the first insulating film;    forming an impurity region of the first general conductivity type in the semiconductor layer under the gate electrode after the formation of the gate electrode;    forming two channel regions of a second general conductivity type in the semiconductor layer so that the impurity region connects the two channel regions;    forming a source region of the first general conductivity type in each of the channel regions; and    forming a second insulating film covering the gate electrode.    
   
   
       8 . A method of manufacturing a semiconductor device, comprising: 
 providing a device intermediate comprising a semiconductor substrate of a first general conductivity type, a semiconductor layer of the first general conductivity type disposed on a surface of the semiconductor substrate and a first insulating film disposed on the semiconductor layer;    forming on the first insulation film a gate electrode having an opening therein;    implanting a first impurity for the first general conductivity type into part of the semiconductor layer through the opening of the gate electrode;    implanting a second impurity for the second general conductivity type into part of the semiconductor layer that is outside the gate electrode;    heating the device intermediate so that the first and second impurities are diffused so as to form an impurity region and a channel region that have an junction interface perpendicular to the surface of the semiconductor substrate;    forming a source region of the first general conductivity type in the channel region; and    forming a second insulating film covering the gate electrode.    
   
   
       9 . The method of  claim 8 , wherein a width of the gate electrode between the opening and an edge of the gate electrode is equal to or less than a depth of the channel region.  
   
   
       10 . The method of  claim 7 , wherein the impurity region and the channel regions have an equal impurity concentration.  
   
   
       11 . The method of  claim 8 , wherein the impurity region and the channel region have an equal impurity concentration.  
   
   
       12 . The method of  claim 10 , wherein the equal impurity concentration is about 1×10 17  cm −3 .  
   
   
       13 . The method of  claim 11 , wherein the equal impurity concentration is about 1×10 17  cm −3 .  
   
   
       14 . The method of  claim 8 , wherein the opening of the gate electrodes creates a separation of two parallel portions of the gate electrode, a ratio of a separation width between the two parallel portions to a depth of the channel region is 0.15 or smaller.  
   
   
       15 . The method of  claim 7 , wherein a bottom of the impurity region and a bottom of each of the channel regions are at a same level.  
   
   
       16 . The method of  claim 8 , wherein a bottom of the impurity region and a bottom of the channel region are at a same level.  
   
   
       17 . The method of  claim 8 , wherein the source region is formed by an ion implantation and a diffusion.  
   
   
       18 . A semiconductor device comprising: 
 a semiconductor substrate of a first general conductivity type;    a semiconductor layer of the first general conductivity type disposed on a surface of the semiconductor substrate so as to provide a drain region;    two channel regions of a second general conductivity type disposed on the semiconductor layer;    an impurity region of the first general conductivity type disposed between the two channel regions so as to connect the two channel regions;    an insulating film disposed on the impurity region;    a gate electrode disposed on the insulating film and comprising a first gate electrode portion and a second gate electrode portion that are disposed on the impurity region between the two channel regions, the first gate electrode portion being at least partially separated from the second gate electrode portion; and    a source region of the first general conductivity type formed in a surface of each of the channel regions.    
   
   
       19 . A semiconductor device comprising: 
 a semiconductor substrate of a first general conductivity type;    a semiconductor layer of the first general conductivity type disposed on a surface of the semiconductor substrate so as to provide a drain region;    two channel regions of a second general conductivity type disposed on the semiconductor layer, each of the channel regions being elongated in a direction;    an impurity region of the first general conductivity type disposed between the two elongated channel regions, the impurity region being elongated in the direction;    an insulating film disposed on the elongated impurity region and channel regions;    a gate electrode disposed on the insulating film and having a slit elongated in the direction but not reaching an edge portion of the gate electrode; and    a source region of the first general conductivity type formed in a surface of each of the channel regions.