Selectively doped trench device isolation

Abstract

A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.

1 . A method of forming an isolation device on a field region of a substrate comprising: 
 forming a trench in the substrate wherein said trench defines a trench surface;    forming a first material layer on said surface wherein said first material is comprised of an insulating material;    filling said trench with a second material having a work function value higher than the work function value of the substrate; and    applying an electrical bias on said second material so as to induce a field threshold voltage into said field region wherein said field threshold voltage inhibits electrical conduction in that field region.    
   
   
       2 . The method of  claim 1 , further comprising forming a mask structure on said substrate prior to forming said trench step.  
   
   
       3 . The method of  claim 2 , further comprising patterning and etching said masking structure.  
   
   
       4 . The method of  claim 2 , wherein the act of forming a mask structure comprises: 
 forming a silicon oxide layer on said substrate; and    depositing a nitride layer on said silicon oxide layer.    
   
   
       5 . The method of  claim 1 , wherein said forming a first material layer on said surface comprises growing an silicon oxide layer on said surface.  
   
   
       6 . The method of  claim 1 , wherein the act of said filling said trench comprises selectively depositing a P+ polysilicon material on said silicon oxide layer wherein said P+ polysilicon material comprises a p-type dopant material having a concentration range of 10 19 -10 21  atoms cm −3 .  
   
   
       7 . The method of  claim 6 , wherein the act of selectively depositing a P+ polysilicon material on said silicon oxide results in forming a channel stop layer between the side walls of said trench and said silicon oxide layer by diffusion of said dopant material into an interface between the side walls of said trench and said silicon oxide layer.  
   
   
       8 . A semiconductor integrated circuit comprising; 
 a semiconductor substrate having a first work function value, said substrate defines a first active area having a first active device and a second active area having a second active device; and    an isolation structure which includes a trench formed in said substrate between said first and second active areas and further includes an insulating layer positioned on the side walls of said trench and a second material filling said trench so that said insulating layer is interposed between the substrate and the second material wherein said second material comprises a material having a second work function value which is greater than the first work function value of said substrate.    
   
   
       9 . The semiconductor integrated circuit of  claim 8 , wherein said substrate is a p-type silicon substrate.  
   
   
       10 . The semiconductor integrated circuit of  claim 8 , wherein said first work function value is approximately 4.9 electron volts.  
   
   
       11 . The semiconductor integrated circuit of  claim 8 , wherein said second work function value is approximately 5.2 electron volts.  
   
   
       12 . The semiconductor integrated circuit of  claim 8 , wherein said insulating layer comprises silicon dioxide (SiO 2 ).  
   
   
       13 . The semiconductor integrated circuit of  claim 8 , wherein said second material is comprised of P+ polysilicon material, said P+ polysilicon material comprises a dopant material with a concentration range of 10 19 -10 21  atoms cm −3 .  
   
   
       14 . The semiconductor integrated circuit of  claim 13 , wherein said dopant material is boron.  
   
   
       15 . The semiconductor integrated circuit of  claim 13 , wherein a channel stop layer is formed at an interface between said trench surface and said insulating layer as a result of diffusion of dopant materials from said P+ polysilicon material into said substrate.  
   
   
       16 . The semiconductor integrated circuit of  claim 15 , wherein the work function difference between the silicon substrate and the P+ polysilicon material induces a threshold voltage sufficient to prevent electrical conduction between said active devices.