Methods of fabricating self-aligned source of flash memory device

Abstract

Example methods of fabricating semiconductor devices are disclosed. One example method may include depositing an oxide layer, a first conducting layer for a floating gate, a dielectric layer, and a second conducting layer for a control gate in sequence on a semiconductor substrate including a device isolation layer; forming gates by removing some parts of the oxide layer, the first conducting layer, the dielectric layer, and the second conducting layer; forming a mask pattern for a self-aligned source over the substrate including the gates; removing the device isolation layer exposed between the gates; performing an ion implantation process; and eliminating damage generated during the ion implantation process or the removal of the device isolation layer.

1 . A semiconductor device, comprising: 
 a semiconductor substrate comprising a trench formed by removing at least a portion of a device isolation layer;    a plurality of gates each comprising an oxide layer, a first conducting layer for a floating gate, a dielectric layer, and a second conducting layer for a control gate, wherein the trench is formed in the semiconductor substrate between the plurality of gates;    a self-aligned source formed by an impurity ion implantation process in the trench and a selective chemical dry etch for eliminating damage resulting from the ion implantation or the removing of at least a portion of a device isolation layer; and    an insulating layer formed over the resulting substrate .    
   
   
       2 . The semiconductor device as defined by  claim 1 , wherein the first conducting layer and the dielectric layer are formed of polysilicon.  
   
   
       3 . The semiconductor device as defined by  claim 1 , wherein the dielectric layer is an oxide-nitride-oxide (ONO) layer.  
   
   
       4 . The semiconductor device as defined by  claim 1 , wherein the first conducting layer is a doped polysilicon formed by depositing a polysilicon layer and implanting ions As or P in the polysilicon layer.  
   
   
       5 . The semiconductor device as defined by  claim 1 , further comprising a silicide layer on the second conducting layer.  
   
   
       6 . The semiconductor device as defined by  claim 1 , wherein the insulating layer is a BPSG (boron phosphorus silicate glass) layer.  
   
   
       7 . The semiconductor device as defined by  claim 1 , wherein the trench is formed by dry etching the device isolation layer.  
   
   
       8 . The semiconductor device as defined by  claim 7 , wherein the dry etching is performed by applying a top power between 800 W and 1500 W under a pressure between 100 mTorr and 300 mTorr.  
   
   
       9 . The semiconductor device as defined by  claim 7 , wherein the dry etching is performed using C 4 F 8  between 3 sccm and 5 sccm, CHF 3  between 2 sccm and 6 sccm, O 2  between 1 sccm and 5 sccm, and Ar between 100 sccm and 300 sccm.  
   
   
       10 . The semiconductor device as defined by  claim 1 , wherein the selective chemical dry etch process employs remote plasma in order to prevent ions from entering into a reaction chamber and to allow reaction only by radicals.  
   
   
       11 . The semiconductor device as defined by  claim 1 , wherein the selective chemical dry etch is an isotropic etching.  
   
   
       12 . The semiconductor device as defined by  claim 1 , wherein the selective chemical dry etch is performed by applying microwave power between 300 W and 500 W under a pressure between 200 mTorr and 250 mTorr.  
   
   
       13 . The semiconductor device as defined by  claim 1 , wherein the selective chemical dry etch is performed using CF 4  between 200 sccm and 280 sccm and O 2  between 40 sccm and 80 sccm.