Non-volatile memory device and method of fabricating the same

Abstract

A non-volatile memory device includes a tunnel oxide layer, a charge storage layer, a blocking insulating layer, and a gate electrode that are sequentially stacked, as well as an impurity diffusion layer in an active region at both sides of the gate electrode. The gate electrode crosses active regions between device isolation layers formed in a predetermined area of a semiconductor substrate, and an edge of the charge storage layer is extended to have a protruding part that protrudes from the gate electrode. In order to form a charge storage layer having a protruding part, a stack insulating layer including first to third insulating layers is formed in an active region between the device isolation layers formed in the substrate. A plurality of gate electrodes crossing the active region are formed on the stack insulating layer, and a sidewall spacer is formed on both sidewalls of the gate electrode. Using the sidewall spacer and the gate electrode, the stack insulating layer is etched to form a charge storage layer that protrudes from the sidewall of the gate electrode.

1 . A method of fabricating a non-volatile memory device, comprising the steps of: 
 forming a stack insulating layer on a semiconductor substrate by sequentially stacking first, second and third insulating layers;    forming a gate electrode crossing over the stack insulating layer; and    forming a charge storage layer and a blocking insulating layer which are sequentially stacked between the gate electrode and the first insulating layer by patterning the third and second insulating layers, wherein at least the second insulating layer is patterned so that the charge storage layer has a protruding part which protrudes from a sidewall of the gate electrode.    
     
     
         2 . The method of  claim 1 , wherein the first and third insulating layers are made of silicon oxide, and the second insulating layer is made of silicon nitride.  
     
     
         3 . The method of  claim 1 , wherein the step of forming the charge storage layer and the blocking insulating layer includes the steps of: 
 etching the third insulating layer by using the gate electrode as an etch mask to form a blocking insulating layer which is self-aligned to the gate electrode;    forming a first sidewall spacer on the sidewall of the gate electrode and a sidewall of the blocking insulating layer; and    etching the second insulating layer by using the gate electrode and the first sidewall spacer as an etch mask to form a charge storage layer whose width is larger than a width of the gate electrode.    
     
     
         4 . The method of  claim 3 , further comprising a steps of forming a gate capping oxide layer at least on the sidewall of the gate electrode prior to formation of the first sidewall spacer.  
     
     
         5 . The method of  claim 3 , further comprising a step of forming a second sidewall spacer on an outer sidewall of the first sidewall spacer and the sidewall of the charge storage layer.  
     
     
         6 . The method of  claim 1 , wherein the step of forming the charge storage layer and the blocking insulating layer includes the steps of: 
 forming a first sidewall spacer on the sidewall of the gate electrode; and    sequentially etching third and second insulating layers by using the gate electrode and the first sidewall spacer to form a blocking insulating layer having a protruding part under the first sidewall spacer and a charge storage layer which is self-aligned to the blocking insulating layer.    
     
     
         7 . The method of  claim 6 , further comprising a step of forming a gate capping oxide layer at least on the sidewall of the gate electrode prior to formation of the first sidewall spacer.  
     
     
         8 . The method of  claim 6 , further comprising a step of forming a second sidewall spacer on the outer sidewall of the first sidewall spacer, the sidewall of the blocking insulating layer, and the sidewall of the charge storage layer.  
     
     
         9 . A method of fabricating a non-volatile memory device, comprising the steps of: 
 forming a device isolation layer and a stack insulating layer, wherein the device isolation layer is formed in a predetermined area of a semiconductor substrate to define an active region, and the stack insulating layer includes first, second and third insulating layers which are sequentially stacked at least on the active region;    forming a gate electrode crossing the active region on the stack insulating layer; and    forming a charge storage layer and a blocking insulating layer which are sequentially stacked between the first insulating layer and the gate electrode by patterning the third to second insulating layers,    wherein at least the second insulating layer is patterned so that the charge storage layer has a protruding part which protrudes from the sidewall of the gate electrode.    
     
     
         10 . The method of  claim 9 , wherein the first and third insulating layers are made of silicon oxide, and the second insulating layer is made of silicon nitride.  
     
     
         11 . The method of  claim 9 , wherein the step of forming the device isolation layer, the stack insulating layer, and the gate electrode includes the steps of: 
 sequentially forming a first insulating layer, a second insulating layer, a third insulating layer, and a lower gate conductive layer on an entire surface of the substrate;    sequentially patterning the lower gate conductive layer, the third insulating layer, the second insulating layer, and the first insulating layer to form a trench region which defines an active region in a predetermined area of the substrate;    forming a device isolation layer to fill the trench area;    forming a lower gate conductive layer on an entire surface of a resultant structure including the device isolation layer; and    sequentially patterning the upper gate conductive layer and the patterned lower gate conductive layer to form a lower gate electrode intervened between the gate electrode and the active region as well as an upper gate electrode crossing over the active region and the device isolation layer.    
     
     
         12 . The method of  claim 9 , wherein the step of forming the device isolation layer, the stack insulating layer, and the gate electrode includes the steps of: 
 forming a device isolation layer to define an active region in a predetermined area of the substrate;    sequentially forming first to third insulating layers and a gate conductive layer on an entire surface of a resultant structure including the device isolation layer; and    patterning the gate conductive layer.    
     
     
         13 . The method of  claim 9 , wherein the step of forming the charge storage layer and the blocking insulating layer includes the steps of: 
 etching the third insulating layer by using the gate electrode as an etch mask to form a blocking insulating layer which is self-aligned to the gate electrode;    forming a first sidewall spacer on the sidewall of the gate electrode and the sidewall of the blocking insulating layer; and    etching the second insulating layer by using the gate electrode and the first sidewall spacer as an etch mask to form a charge storage layer whose width is larger than a width of the gate electrode.    
     
     
         14 . The method of  claim 13 , further comprising a step of forming a gate capping oxide layer at least on the sidewall of the gate electrode prior to formation of the first sidewall spacer.  
     
     
         15 . The method of  claim 13 , further comprising a step of forming a second sidewall spacer on the outer sidewall of the first sidewall spacer and the sidewall of the charge storage layer.  
     
     
         16 . The method of  claim 9 , wherein the step of forming the charge storage layer and the blocking insulating layer includes the steps of: 
 forming a first sidewall spacer on the sidewall of the gate electrode; and    sequentially etching the third and second insulating layers by using the gate electrode and the first sidewall spacer as an etch mask to form a blocking insulating layer having a protruding part under the first sidewall spacer and a charge storage layer which is self-aligned to the blocking insulating layer.    
     
     
         17 . The method of  claim 16 , further comprising a step of forming a gate capping oxide layer at least on the sidewall of the gate electrode prior to formation of the first sidewall spacer.  
     
     
         18 . The method of  claim 16 , further comprising a step of forming a second sidewall spacer on the outer sidewall of the first sidewall spacer, the sidewall of the blocking insulating layer, and the sidewall of the charge storage layer.  
     
     
         19 . A method of fabricating a non-volatile memory device with a cell array region and a peripheral circuit region, comprising the steps of: 
 forming not only a device isolation layer in a predetermined area of a semiconductor substrate to define a first active region and a second active region in the cell array region and the peripheral circuit region, respectively, but also a stack insulating layer including first, second and third insulating layers which are sequentially stacked on the first active region, and a gate insulating layer stacked on the second active region;    forming a plurality of wordlines crossing over the stack insulating layer, and a gate electrode crossing over the gate insulating layer; and    patterning at least the third and second insulating layers to form a charge storage layer and a blocking insulating layer which are sequentially stacked between the first insulating layer and the wordlines,    wherein at least the second insulating layer is patterned so that the charge storage layer has a protruding part which protrudes from a sidewall of the wordlines.    
     
     
         20 . The method of  claim 19 , wherein the first and third insulating layers are made of silicon oxide, and the second insulating layer is made of silicon nitride.  
     
     
         21 . The method of  claim 19 , wherein the step of forming the device isolation layer, the stack insulating layer, the gate insulating layer, the wordlines, and the gate electrode includes the steps of: 
 selectively forming the stack insulating layer on the substrate in the cell array region;    selectively forming a gate insulating layer on the substrate in the peripheral circuit region;    forming a lower gate conductive layer under a resultant structure including the gate insulating layer;    sequentially patterning the lower conductive layer, the stack insulating layer, the gate insulating layer, and the substrate to form a trench area which defines a first active region and a second active region in the cell array region and the peripheral circuit region, respectively;    forming a device isolation layer to fill the trench area;    forming an upper gate conductive layer on an entire surface of a resultant structure including the device isolation layer; and    forming a plurality of wordlines crossing over the upper gate conductive layer, and a gate electrode crossing over the second active region,    wherein each of the wordlines includes an upper wordline crossing over the first active region, and a lower wordline intervened between the upper wordline and the first active region; and    wherein the gate electrode includes an upper gate electrode crossing over the second active region, and a lower gate electrode intervened between the upper gate electrode and the second active region.    
     
     
         22 . The method of  claim 19 , wherein the step of forming the device isolation layer, the stack insulating layer, the gate insulating layer, the wordlines, and the gate electrode includes the steps of: 
 forming a device isolation layer in a predetermined area of the substrate to define a first active region and a second active region in the cell array region and the peripheral circuit region, respectively;    selectively forming first, second and third insulating layers in the cell array region of a resultant structure including the device isolation layer;    forming a gate insulating layer on the second active region;    forming a conductive layer on an entire surface of a resultant structure including the first to third insulating layers and the gate insulating layer; and    patterning the conductive layer to form wordlines crossing the first active region and a gate electrode crossing the second active region.    
     
     
         23 . The method of  claim 19 , wherein the step of forming the charge storage layer and the blocking insulating layer includes the steps of: 
 etching the third insulating layer by using the wordlines as an etch mask to form blocking insulating layers which are self-aligned to the wordlines;    forming a first sidewall spacer on sidewalls of the wordlines, sidewalls of the blocking insulating layers, and the sidewall of the gate electrode; and    etching the second insulating layer by using the wordlines and the first sidewall spacer as an etch mask to form a charge storage layer whose width is larger than a width of the wordline.    
     
     
         24 . The method of  claim 23 , further comprising a step of forming a gate capping oxide layer on surfaces of the wordlines and a surface of the gate electrode prior to formation of the first sidewall spacer.  
     
     
         25 . The method of  claim 23 , further comprising a step of implanting impurities into the second active region by using the gate electrode and the first sidewall spacer as an ion implanting mask to form a heavily doped source/drain region, before or after forming the charge storage layer.  
     
     
         26 . The method of  claim 25 , further comprising a step of implanting impurities into the first and second active regions by using the wordlines and the gate electrode as an ion implanting mask, before or after forming the blocking insulating layer.  
     
     
         27 . The method of  claim 23 , further comprising a step of forming a second sidewall spacer on the outer sidewall of the first sidewall spacer and the sidewall of the charge storage layer in the cell array region, and on an outer sidewall of the first sidewall spacer in the peripheral circuit region.  
     
     
         28 . The method of  claim 27 , further comprising a step of implanting impurities into the second active region by using the gate electrode, the first sidewall spacer, and the second sidewall spacer as an ion implanting mask to form a heavily doped source/drain region.  
     
     
         29 . The method of  claim 28 , further comprising a step of implanting impurities into the first and second active regions by using the wordlines and the gate electrode as an ion implanting mask to form a lightly doped source/drain region.  
     
     
         30 . The method of  claim 28 , further comprising a step of implanting impurities into the first and second active regions by using the wordlines, the gate electrode, and the first sidewall spacer as an ion implanting mask to form a lightly doped source/drain region.  
     
     
         31 . The method of  claim 19 , wherein the step of forming the charge storage layer and the blocking insulating layer includes the steps of: 
 forming a first sidewall spacer on the sidewalls of the wordlines and the sidewall of the gate electrode; and    sequentially etching the third and second insulating layers by using the gate electrode, the first sidewall spacer, and the first sidewall spacer as an etch mask to form a blocking insulating layer having a protruding part under the first sidewall spacer and a charge storage layer that is self-aligned to the blocking insulating layer.    
     
     
         32 . The method of  claim 31 , further comprising a step of a gate capping oxide layer on the surface of the gate electrode and the surfaces of the wordlines prior to formation of the first sidewall spacer.  
     
     
         33 . The method of  claim 31 , further comprising a step of implanting impurities into the second active region by using the wordlines, the gate electrode, and the first sidewall spacer as an ion implanting mask to form a heavily doped source/drain region, following formation of the first sidewall spacer.  
     
     
         34 . The method of  claim 33 , further comprising a step of implanting impurities into the first and second active regions by using the wordlines and the gate electrode as an ion implanting mask to form a lightly doped source/drain region, prior to formation of the first sidewall spacer.  
     
     
         35 . The method of  claim 31 , further comprising a step of forming a second sidewall spacer on the outer sidewall of the first sidewall spacer, the sidewall of the charge storage layer, and the sidewall of the blocking insulating layer in the cell array region, and on the outer sidewall of the first sidewall spacer in the peripheral circuit region.  
     
     
         36 . The method of  claim 35 , further comprising a step of implanting impurities into the second active region by using the gate electrode, the first sidewall spacer, and the second sidewall spacer as an ion implanting mask to form a heavily doped source/drain region.  
     
     
         37 . The method of  claim 36 , further comprising a step of implanting impurities into the first and second active regions by using the wordlines and the gate electrode as an ion implanting mask to form a lightly doped source/drain region, prior to formation of the first sidewall spacer.  
     
     
         38 . The method of  claim 36 , further comprising a step of implanting impurities into the first and second active regions by using the wordlines, the gate electrode, and the first sidewall spacer as an ion implanting mask to form a light doped source/drain region, before or after forming the charge storage layer and the blocking insulating layer.