High coupling memory cell

Abstract

A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first conductive layer to increase the capacitive coupling of the floating gate with a control gate. An intergate dielectric layer is formed over the floating gate layer. A second conductive layer is formed over the second dielectric layer to act as a control gate.

1 . A method for fabricating a memory cell, the method comprising: 
 forming a first dielectric layer over a substrate;    forming a floating gate over the first dielectric layer;    forming a trough in the floating gate;    forming a second dielectric layer over the floating gate; and    forming a control gate over the second dielectric layer.    
   
   
       2 . The method of  claim 1  wherein the floating gate is comprised of doped polysilicon.  
   
   
       3 . The method of  claim 1  and further including performing shallow trench isolation to form isolation trenches between each trough, the isolation trenches comprising dielectric material.  
   
   
       4 . The method of  claim 3  wherein the floating gate is formed such that the top of the floating gate is substantially even with the dielectric material in the isolation trenches.  
   
   
       5 . The method of  claim 1  wherein the first dielectric layer comprises an oxide.  
   
   
       6 . The method of  claim 1  wherein the second dielectric layer comprises an oxide-nitride-oxide composite layer.  
   
   
       7 . The method of  claim 1  wherein the second dielectric layer comprises a nitride-oxide composite layer.  
   
   
       8 . The method of  claim 1  wherein the control gate comprises a doped polysilicon.  
   
   
       9 . The method of  claim 1  wherein forming the trough comprises: 
 patterning the floating gate to produce exposed areas that are susceptible to etching; and    removing a portion of the exposed areas.    
   
   
       10 . A method for fabricating a memory cell in a memory array, the method comprising: 
 forming a first dielectric layer over a substrate;    forming a plurality of isolation trenches in the first dielectric layer and substrate, 
 each isolation trench filled with an insulator material having an upper  
 portion that extends above the first dielectric layer;  
   forming a floating gate over the first dielectric layer and around the upper portions;    forming troughs in the floating gate;    forming a second dielectric layer over the floating gate; and    forming a control gate over the second dielectric layer.    
   
   
       11 . The method of  claim 10  wherein the plurality of isolation trenches separate source and drain areas of the memory cell.  
   
   
       12 . The method of  claim 10  and further including: 
 forming a pad oxide layer over the substrate;    removing the pad oxide with an isotropic strip process; and    reducing the thickness of the upper portions to create a substantially concave shape to each side of each upper portion.    
   
   
       13 . The method of  claim 10  wherein the floating gate is an insitu doped polysilicon.  
   
   
       14 . The method of  claim 12  and further including forming a sacrificial layer over the pad oxide layer that acts as a polishing stop layer during a chemical mechanical polishing process.  
   
   
       15 . The method of  claim 10  and further including coupling the control gate to a wordline of the memory array.  
   
   
       16 . The method of  claim 10  wherein forming the troughs comprises etching the floating gate for a predetermined time that determines the depth of the troughs.  
   
   
       17 . The method of  claim 10  wherein the floating gate is formed by a deposition process.  
   
   
       18 . The method of  claim 10  wherein forming troughs further comprises creating a multi-level trough.  
   
   
       19 . A memory cell comprising: 
 a first dielectric layer formed over a substrate;    a plurality of isolation trenches formed in the tunnel dielectric layer and substrate;    a floating gate formed over the first dielectric layer;    a trough formed in the floating gate;    a second dielectric layer formed over the floating gate; and    a control gate formed over the second dielectric layer.    
   
   
       20 . The memory cell of  claim 19  wherein the second dielectric layer is comprised of one of an oxide-nitride-oxide composite or a nitride-oxide composite.  
   
   
       21 . A non-volatile memory device comprising: 
 a plurality of first dielectric layers formed over a substrate;    a plurality of isolation trenches formed between each of the first dielectric layers and in the substrate;    a plurality of floating gates, each having multi-level troughs, formed over each of the first dielectric layers and between each pair of isolation trenches;    a second dielectric layer formed over each floating gate; and    a control gate formed over each second dielectric layer.    
   
   
       22 . A memory system comprising: 
 a processor that generates memory signals; and    a memory device coupled to the processor and comprising a memory array having a 
 plurality of memory cells, each memory cell comprising:  
 a tunnel dielectric layer formed over a substrate;  
 a plurality of isolation trenches formed in the tunnel dielectric layer and substrate;  
 a floating gate formed over the tunnel dielectric layer;  
 a trough formed in the floating gate;  
 an intergate dielectric layer formed over the floating gate; and  
 a control gate formed over the intergate dielectric layer.  
   
   
   
       23 . The system of  claim 22  wherein the memory array is comprised of one of a NAND-architecture or a NOR architecture.