Graphics Controller Integrated Circuit without Memory Interface

Abstract

A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

1 . A complementary MOS integrated circuit, containing NMOS transistors and PMOS transistors, comprising 
 circuitry for processing, controlling or manipulating data of an electronic system interconnected with said complementary MOS integrated circuit, said circuitry including at least 30K logic gates, said circuitry further including an n-bit graphics processor with the number “n” being either 32 or 64 bits;    a memory for storing and retrieving at least a portion of said data, said memory having a capacity of at least 2 megabits; and    a data interface located between said data processing, controlling or manipulating circuitry and said memory, said data interface being “m” bits wide, where the number “m” is a multiple of the number “n” and the number “m” is at least twice as large as the number “n”;    whereby the integration of the multiple functions performed by said circuitry, said memory and said data interface into single said complementary MOS integrated circuit can result in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.    
     
     
         2 . A complementary MOS integrated circuit, containing NMOS transistors and PMOS transistors, comprising 
 circuitry for processing, controlling or manipulating data of an electronic system interconnected with said complementary MOS integrated circuit, said circuitry including at least 30K logic gates, said circuitry further including an n-bit processor, or processing element, with the number “n” being either 32 or 64 bits;    a memory for storing and retrieving at least a portion of said data, said memory having a capacity of at least 2 megabits; and    a data interface located between said data processing, controlling or manipulating circuitry and said memory, said data interface being “m” bits wide, where the number “m” is a multiple of the number “n” and the number “m” is at least twice as large as the number “n”;    whereby the integration of the multiple functions performed by said circuitry, said memory and said data interface into single said complementary MOS integrated circuit can result in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.    
     
     
         3 . A complementary MOS integrated circuit, containing NMOS transistors and PMOS transistors, comprising 
 circuitry for processing, controlling or manipulating data of an electronic system interconnected with said complementary MOS integrated circuit, said circuitry including at least 30K logic gates, said circuitry including graphics operational circuitry processing, controlling or manipulating said data up to 64 bits at time;    a memory for storing and retrieving at least a portion of said data, said memory having a capacity of at least 2 megabits; and    a data interface located between said data processing, controlling or manipulating circuitry and said memory, said data interface being “m” bits wide, where the number “m” is a multiple of the number “64” and the number “m” is at least twice as large as the number “64”;    whereby the integration of the multiple functions performed by said circuitry, said memory and said data interface into single said complementary MOS integrated circuit can result in a lower number of integrated circuit packages, and lower power dissipation, in said electronic system in which said complementary MOS integrated circuit resides.    
     
     
         4 . The complementary MOS integrated circuit of  claim 3  wherein said graphics operational circuitry includes a Bit Block Transfer operation unit performing operations upon said data up to a predetermined number of bits at a time responsive to instructions.  
     
     
         5 . The complementary MOS integrated circuit of  claim 4  wherein said Bit Block Transfer operation unit performs operations upon said data 64 bits at a time responsive to instructions.  
     
     
         6 . The complementary MOS integrated circuit of  claim 4  wherein said graphics operational circuitry includes a graphics controller unit.  
     
     
         7 . The complementary MOS integrated circuit of  claim 6  wherein said graphics controller unit can selectively load a single, or multiple, bytes, to said data interface at one time.